{"id":7933,"date":"2026-06-28T05:54:01","date_gmt":"2026-06-28T05:54:01","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls86n\/"},"modified":"2026-06-28T11:45:48","modified_gmt":"2026-06-28T11:45:48","slug":"sn74ls86n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74ls86n\/","title":{"rendered":"SN74LS86N"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The SN74LS86N from Texas Instruments is a quad 2-input exclusive-OR (XOR) gate with LS TTL technology, 14ns propagation delay, and industry-standard 7486 pinout in a 14-pin PDIP package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n
Number of Gates<\/td>\n4 (quad 2-input XOR)<\/td>\n<\/tr>\n
\u903b\u8f91\u5bb6\u65cf<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
\u4f20\u64ad\u5ef6\u8fdf<\/td>\n14ns typical @ 5V<\/td>\n<\/tr>\n
Output Drive (IOL\/IOH)<\/td>\n8mA \/ -0.4mA<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • Four independent 2-input XOR gates<\/li>\n
  • LS TTL technology<\/li>\n
  • 14ns typical propagation delay<\/li>\n
  • Industry-standard 7486 pinout<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Parity generation and checking<\/li>\n
    • Two’s complement subtraction (with adder)<\/li>\n
    • Controlled inversion<\/li>\n
    • Comparator circuits<\/li>\n
    • Frequency doubling<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS86N from Texas Instruments is a quad 2-input exclusive-OR (XOR) gate with LS TTL technology, 14ns propagation delay, and industry-standard 7486 pinout in a 14-pin PDIP package. Key Specifications Number of Gates 4 (quad 2-input XOR) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Propagation Delay 14ns typical […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7933","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Quad 2-input XOR gate, LS TTL, 14ns, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":5200,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls86.pdf","price":"$0.35 @ 1ku","product_introduction":"The SN74LS86N from Texas Instruments contains four independent 2-input exclusive-OR (XOR) gates in a 14-pin PDIP package. Each gate performs the Boolean function Y = A XOR B; the output is HIGH when the inputs are different (01 or 10) and LOW when they are the same (00 or 11). The XOR gate is essential for arithmetic circuits: in an adder, XOR generates the sum bit; in a subtractor, XOR complements the subtrahend under control of a mode signal. When one input is used as a control, the XOR acts as a controlled inverter: if the control is HIGH, the data is inverted; if LOW, the data passes through unchanged. The XOR also serves as a 1-bit comparator: the output is HIGH when the two inputs differ. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each XOR gate in the SN74LS86N performs Y = A XOR B = A \u2295 B. The truth table is: 00\u21920, 01\u21921, 10\u21921, 11\u21920. The output is HIGH when exactly one input is HIGH (exclusive OR). This is equivalent to Y = (A AND NOT-B) OR (NOT-A AND B), or more compactly Y = A \u2295 B. The XOR can also be expressed as Y = (A OR B) AND NOT(A AND B), which is OR minus AND. When input B is used as a control signal: if B=0, Y=A (data passes through); if B=1, Y=NOT-A (data is inverted). This controlled inversion is the basis for two's complement subtraction: to compute A-B, set the control to 1 (complementing B) and feed the result into an adder with carry-in = 1. For parity generation, XOR all data bits together; the result is the parity bit. For parity checking, XOR all data bits plus the parity bit; if the result is 1, a parity error has occurred.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1A<\/td>Input<\/td>Gate 1 input A<\/td><\/tr>\n
      2<\/td>1B<\/td>Input<\/td>Gate 1 input B<\/td><\/tr>\n
      3<\/td>1Y<\/td>Output<\/td>Gate 1 output (XOR)<\/td><\/tr>\n
      4<\/td>2A<\/td>Input<\/td>Gate 2 input A<\/td><\/tr>\n
      5<\/td>2B<\/td>Input<\/td>Gate 2 input B<\/td><\/tr>\n
      6<\/td>2Y<\/td>Output<\/td>Gate 2 output (XOR)<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>3Y<\/td>Output<\/td>Gate 3 output (XOR)<\/td><\/tr>\n
      9<\/td>3A<\/td>Input<\/td>Gate 3 input A<\/td><\/tr>\n
      10<\/td>3B<\/td>Input<\/td>Gate 3 input B<\/td><\/tr>\n
      11<\/td>4Y<\/td>Output<\/td>Gate 4 output (XOR)<\/td><\/tr>\n
      12<\/td>4A<\/td>Input<\/td>Gate 4 input A<\/td><\/tr>\n
      13<\/td>4B<\/td>Input<\/td>Gate 4 input B<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Controlled Inverter:<\/strong> B input = SUB control; when B=1, output = NOT-A (invert for subtraction); when B=0, output = A (pass for addition)<\/li>\n
      • Parity Generator:<\/strong> XOR all 8 data bits together; output is even parity bit; detect single-bit errors<\/li>\n
      • Bit Comparator:<\/strong> XOR corresponding bits of two words; if all XOR outputs = 0, the words are equal<\/li>\n
      • Frequency Doubler:<\/strong> Feed signal to one input, delayed version to other; output pulses on every edge<\/li>\n
      • Adder Sum:<\/strong> XOR of A and B gives sum bit (without carry); pair with AND for carry = half adder<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS86N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS86D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC86D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC86N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT86D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT86N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC86D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC86N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC86D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC86N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7486 is a Quad 2-Input Exclusive-OR Gate. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7933","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7933"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7933\/revisions"}],"predecessor-version":[{"id":8185,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7933\/revisions\/8185"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7933"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7933"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7933"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7933"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}