{"id":7926,"date":"2026-06-28T04:28:53","date_gmt":"2026-06-28T04:28:53","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls283n\/"},"modified":"2026-06-28T11:45:57","modified_gmt":"2026-06-28T11:45:57","slug":"sn74ls283n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74ls283n\/","title":{"rendered":"SN74LS283N"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The SN74LS283N from Texas Instruments is a 4-bit binary full adder with fast carry lookahead, performing addition of two 4-bit binary numbers plus a carry-in, producing a 4-bit sum and carry-out in a 16-pin PDIP package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n
\u529f\u80fd<\/td>\n4-bit binary full adder with carry lookahead<\/td>\n<\/tr>\n
\u903b\u8f91\u5bb6\u65cf<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
Inputs<\/td>\nTwo 4-bit words (A1-A4, B1-B4) + Carry-In (C0)<\/td>\n<\/tr>\n
Outputs<\/td>\n4-bit sum (\u03a31-\u03a34) + Carry-Out (C4)<\/td>\n<\/tr>\n
Addition Time (C0 to C4)<\/td>\n10ns typical (carry propagation)<\/td>\n<\/tr>\n
Addition Time (A\/B to \u03a3)<\/td>\n25ns typical<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • 4-bit binary addition with carry lookahead<\/li>\n
  • Two independent 4-bit word inputs<\/li>\n
  • Carry-in and carry-out for cascading<\/li>\n
  • Fast carry propagation: 10ns typical<\/li>\n
  • Full lookahead for minimum addition time<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Arithmetic logic unit (ALU) implementation<\/li>\n
    • Address calculation and incrementing<\/li>\n
    • Multi-bit addition and subtraction<\/li>\n
    • Digital signal processing arithmetic<\/li>\n
    • Counter and accumulator circuits<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS283N from Texas Instruments is a 4-bit binary full adder with fast carry lookahead, performing addition of two 4-bit binary numbers plus a carry-in, producing a 4-bit sum and carry-out in a 16-pin PDIP package. Key Specifications Function 4-bit binary full adder with carry lookahead Logic Family LS (Low-power Schottky) Supply Voltage […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7926","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"4-bit binary full adder, carry lookahead, C0\/C4 cascade, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":3500,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls283.pdf","price":"$0.65 @ 1ku","product_introduction":"The SN74LS283N from Texas Instruments is a 4-bit binary full adder that adds two 4-bit binary numbers (A1-A4 and B1-B4) and a carry-in (C0) to produce a 4-bit sum (\u03a31-\u03a34) and a carry-out (C4). The carry-lookahead architecture generates the carry-out internally in only 10ns, much faster than a ripple-carry adder where the carry must propagate through all four stages sequentially. This makes the 74LS283 suitable for building wider adders by cascading multiple devices: two 74LS283s create an 8-bit adder by connecting the C4 of the lower-order adder to the C0 of the higher-order adder, with a total carry propagation of only 20ns (10ns per stage). For subtraction, the B input is complemented (using inverters or XOR gates) and C0 is set HIGH, implementing two's complement subtraction. The N suffix denotes the PDIP-16 through-hole package.","working_principle":"The SN74LS283N performs binary addition using carry-lookahead logic. The sum bits are computed as \u03a3i = Ai XOR Bi XOR Ci, and the carry bits as Ci+1 = (Ai AND Bi) OR (Ci AND (Ai XOR Bi)). In a simple ripple-carry adder, each carry bit must be computed sequentially, creating a propagation delay proportional to the number of bits. The 74LS283 avoids this by computing the carry-lookahead functions in parallel: it generates generate (Gi = Ai AND Bi) and propagate (Pi = Ai XOR Bi) signals for all four bits, then computes C4 = G4 + P4\u00b7G3 + P4\u00b7P3\u00b7G2 + P4\u00b7P3\u00b7P2\u00b7G1 + P4\u00b7P3\u00b7P2\u00b7P1\u00b7C0 using only two levels of logic. This reduces the carry propagation from 4 gate delays to just 2. The sum bits are then computed using the pre-computed carries. For multi-bit addition, the C4 output connects to the C0 input of the next 74LS283. For 16-bit addition, four devices are cascaded with a total carry propagation of 40ns (10ns \u00d7 4 stages).","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>\u03a34<\/td>Output<\/td>Sum bit 4 (MSB)<\/td><\/tr>\n
      2<\/td>\u03a33<\/td>Output<\/td>Sum bit 3<\/td><\/tr>\n
      3<\/td>A3<\/td>Input<\/td>Input A bit 3<\/td><\/tr>\n
      4<\/td>B3<\/td>Input<\/td>Input B bit 3<\/td><\/tr>\n
      5<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n
      6<\/td>\u03a32<\/td>Output<\/td>Sum bit 2<\/td><\/tr>\n
      7<\/td>B2<\/td>Input<\/td>Input B bit 2<\/td><\/tr>\n
      8<\/td>A2<\/td>Input<\/td>Input A bit 2<\/td><\/tr>\n
      9<\/td>\u03a31<\/td>Output<\/td>Sum bit 1 (LSB)<\/td><\/tr>\n
      10<\/td>A1<\/td>Input<\/td>Input A bit 1 (LSB)<\/td><\/tr>\n
      11<\/td>B1<\/td>Input<\/td>Input B bit 1 (LSB)<\/td><\/tr>\n
      12<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      13<\/td>C0<\/td>Input<\/td>Carry input (from lower-order adder)<\/td><\/tr>\n
      14<\/td>A4<\/td>Input<\/td>Input A bit 4 (MSB)<\/td><\/tr>\n
      15<\/td>B4<\/td>Input<\/td>Input B bit 4 (MSB)<\/td><\/tr>\n
      16<\/td>C4<\/td>Output<\/td>Carry output (to higher-order adder)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • 8-Bit Adder:<\/strong> Two 74LS283s cascaded; lower C4 \u2192 upper C0; 8-bit A + 8-bit B \u2192 8-bit sum + carry<\/li>\n
      • Subtractor:<\/strong> B inputs through XOR gates (controlled by SUB signal); C0 = SUB; when SUB=1, result = A - B<\/li>\n
      • Address Increment:<\/strong> B = 0001, C0 = 0; \u03a3 = A + 1 (program counter increment)<\/li>\n
      • ALU Core:<\/strong> 74LS283 for addition; XOR for subtraction; AND\/OR for logic; multiplexers select operation<\/li>\n
      • Accumulator:<\/strong> D inputs from \u03a3 outputs; clock captures result; feedback to A for running sum<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS283N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS283D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC283D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC283N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT283D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT283N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n<\/table>\n

        The 74283 is a 4-Bit Binary Full Adder. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7926","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7926"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7926\/revisions"}],"predecessor-version":[{"id":8188,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7926\/revisions\/8188"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7926"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7926"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7926"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7926"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}