{"id":7914,"date":"2026-06-28T04:21:28","date_gmt":"2026-06-28T04:21:28","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls148n\/"},"modified":"2026-06-28T11:46:10","modified_gmt":"2026-06-28T11:46:10","slug":"sn74ls148n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74ls148n\/","title":{"rendered":"SN74LS148N"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The SN74LS148N is an 8-line to 3-line priority encoder from Texas Instruments with active-low inputs\/outputs, cascading capability, and group signal outputs in a 16-pin PDIP package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\u529f\u80fd<\/td>\n8-line to 3-line priority encoder<\/td>\n<\/tr>\n
\u903b\u8f91\u5bb6\u65cf<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
Inputs<\/td>\n8 active-low (0-7), 1 enable (EI, active-low)<\/td>\n<\/tr>\n
Outputs<\/td>\n3 active-low (A2, A1, A0), GS, EO<\/td>\n<\/tr>\n
Priority<\/td>\nInput 7 is highest priority<\/td>\n<\/tr>\n
\u4f20\u64ad\u5ef6\u8fdf<\/td>\n15ns typical (data to output)<\/td>\n<\/tr>\n
Enable Input (EI)<\/td>\nActive-low (device enabled when EI=LOW)<\/td>\n<\/tr>\n
Group Signal (GS)<\/td>\nActive-low (asserted when any input is active)<\/td>\n<\/tr>\n
Enable Output (EO)<\/td>\nActive-low (asserted when no input is active)<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • 8-line to 3-line priority encoder with active-low I\/O<\/li>\n
  • Priority: input 7 has highest, input 0 lowest<\/li>\n
  • Cascading via EI and EO for expanded encoding<\/li>\n
  • Group signal (GS) indicates at least one active input<\/li>\n
  • Enable input (EI) for device selection<\/li>\n
  • Standard 74LS148 pinout<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Keyboard encoding<\/li>\n
    • Interrupt vector generation<\/li>\n
    • Priority interrupt encoding for CPUs<\/li>\n
    • Data compression and encoding<\/li>\n
    • Cascaded multi-chip encoding systems<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS148N is an 8-line to 3-line priority encoder from Texas Instruments with active-low inputs\/outputs, cascading capability, and group signal outputs in a 16-pin PDIP package. Key Specifications Function 8-line to 3-line priority encoder Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Inputs 8 active-low (0-7), 1 enable (EI, […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7914","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"8-to-3 priority encoder, active-low, cascade EI\/EO\/GS, LS TTL, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":4500,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls148.pdf","price":"$0.62 @ 1ku","product_introduction":"The SN74LS148N from Texas Instruments is an 8-line to 3-line priority encoder that converts one of eight active-low input lines to a 3-bit binary output code. When multiple inputs are active simultaneously, the encoder outputs the code for the highest-priority input (input 7 is highest, input 0 is lowest). All inputs and outputs are active-low, simplifying connection to microprocessor interrupt systems that use active-low signals. The enable input (EI, active-low) activates the device; when EI is HIGH, all outputs are HIGH (inactive). The group signal (GS) output goes LOW when any input is active and the device is enabled, indicating a valid encoded output. The enable output (EO) goes LOW only when no inputs are active and the device is enabled. GS and EO facilitate cascading: for a 16-to-4 encoder, two 148s are used with the lower-priority device's EO connected to the higher-priority device's EI. The N suffix denotes the PDIP-16 through-hole package.","working_principle":"The SN74LS148N continuously evaluates the eight input lines (0-7, active-low). If input 7 is LOW (active), the outputs A2,A1,A0 = L,L,L (binary 7, active-low encoded as 000) regardless of the states of inputs 0-6. If input 7 is HIGH (inactive) and input 6 is LOW, the outputs = L,L,H (binary 6). This priority chain continues down to input 0, which only gets encoded if no higher-priority input is active. When the enable input (EI) is HIGH, the device is disabled: all data outputs (A0-A2) are HIGH, GS is HIGH, and EO is HIGH. When EI is LOW and at least one input is active, GS = LOW (indicating a valid encoding) and EO = HIGH. When EI is LOW and no inputs are active, GS = HIGH and EO = LOW. For cascading two devices to create a 16-to-4 encoder: the higher-priority device (inputs 8-15) has its EI connected to the system enable, and its EO connected to the lower-priority device's EI. The GS outputs of both devices are NANDed to form the MSB (A3) of the 4-bit output. The A0-A2 outputs of both devices are ORed (wire-AND for active-low) to form the lower 3 bits.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>4<\/td>Input<\/td>Input line 4 (active low)<\/td><\/tr>\n
      2<\/td>5<\/td>Input<\/td>Input line 5 (active low)<\/td><\/tr>\n
      3<\/td>6<\/td>Input<\/td>Input line 6 (active low)<\/td><\/tr>\n
      4<\/td>7<\/td>Input<\/td>Input line 7 (active low, highest priority)<\/td><\/tr>\n
      5<\/td>EO<\/td>Output<\/td>Enable output (active low, =LOW when no input active)<\/td><\/tr>\n
      6<\/td>GS<\/td>Output<\/td>Group signal (active low, =LOW when any input active)<\/td><\/tr>\n
      7<\/td>A2<\/td>Output<\/td>Encoded output MSB (active low)<\/td><\/tr>\n
      8<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>A1<\/td>Output<\/td>Encoded output middle bit (active low)<\/td><\/tr>\n
      10<\/td>A0<\/td>Output<\/td>Encoded output LSB (active low)<\/td><\/tr>\n
      11<\/td>0<\/td>Input<\/td>Input line 0 (active low, lowest priority)<\/td><\/tr>\n
      12<\/td>1<\/td>Input<\/td>Input line 1 (active low)<\/td><\/tr>\n
      13<\/td>2<\/td>Input<\/td>Input line 2 (active low)<\/td><\/tr>\n
      14<\/td>3<\/td>Input<\/td>Input line 3 (active low)<\/td><\/tr>\n
      15<\/td>EL<\/td>Input<\/td>Enable input (active low)<\/td><\/tr>\n
      16<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Interrupt Encoder:<\/strong> 8 interrupt sources into 3-bit vector; GS connects to MCU \/IRQ pin; A0-A2 read as interrupt ID<\/li>\n
      • Keyboard Encoder:<\/strong> 8 keys into 3-bit code; priority resolves simultaneous key presses<\/li>\n
      • 16-Input Encoder:<\/strong> Cascade two 148s for 16-to-4 encoding; higher-priority EO drives lower EI<\/li>\n
      • Priority Detection:<\/strong> GS output indicates any request; MCU reads A0-A2 only when GS=LOW<\/li>\n
      • Data Compression:<\/strong> Encode 8 binary inputs into 3 bits for bus width reduction<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS148N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS148D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC148D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC148N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT148D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT148N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n<\/table>\n

        The 74148 is a 8-Line to 3-Line Priority Encoder. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7914","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7914"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7914\/revisions"}],"predecessor-version":[{"id":8194,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7914\/revisions\/8194"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7914"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7914"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7914"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7914"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}