{"id":7847,"date":"2026-06-28T02:48:25","date_gmt":"2026-06-28T02:48:25","guid":{"rendered":"https:\/\/materialparts.com\/cd4013be\/"},"modified":"2026-06-28T10:09:45","modified_gmt":"2026-06-28T10:09:45","slug":"cd4013be","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/cd4013be\/","title":{"rendered":"CD4013BE"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The CD4013BE is a dual D-type flip-flop from Texas Instruments with independent set and reset, static and clocked operation, and 10MHz typical toggle frequency in a 14-pin PDIP package.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Number of Flip-Flops<\/td>\n2 (dual, independent)<\/td>\n<\/tr>\n
Supply Voltage Range<\/td>\n3V to 15V<\/td>\n<\/tr>\n
Toggle Frequency<\/td>\n10MHz typical at 10V, 4MHz at 5V<\/td>\n<\/tr>\n
Clock Pulse Width<\/td>\n40ns typical at 10V<\/td>\n<\/tr>\n
Setup Time<\/td>\n15ns typical at 10V<\/td>\n<\/tr>\n
Hold Time<\/td>\n5ns typical at 10V<\/td>\n<\/tr>\n
Input Current<\/td>\n1\u00b5A typical at 10V<\/td>\n<\/tr>\n
Output Drive<\/td>\n1.3mA sink\/source at 5V<\/td>\n<\/tr>\n
\u9759\u6001\u7535\u6d41<\/td>\n2\u00b5A typical per package at 5V<\/td>\n<\/tr>\n
Set\/Reset<\/td>\nActive high, independent, asynchronous<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n-55\u00b0C to +125\u00b0C<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nPDIP-14 (19.3 x 6.35mm, through-hole)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • Two independent D-type flip-flops in one package<\/li>\n
  • Asynchronous set (S) and reset (R) inputs, active high<\/li>\n
  • Data transfers to output on positive clock edge<\/li>\n
  • Wide supply voltage range: 3V to 15V<\/li>\n
  • Standard CMOS input and output levels<\/li>\n
  • Very low quiescent current: 2\u00b5A typical at 5V<\/li>\n
  • Military temperature range: -55\u00b0C to +125\u00b0C<\/li>\n
  • Direct replacement for CD4013 and MC14013<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Frequency dividers and counters<\/li>\n
    • Shift registers and data storage<\/li>\n
    • Toggle flip-flops for timing circuits<\/li>\n
    • Control and sequencing logic<\/li>\n
    • Debouncing and synchronization circuits<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The CD4013BE is a dual D-type flip-flop from Texas Instruments with independent set and reset, static and clocked operation, and 10MHz typical toggle frequency in a 14-pin PDIP package. Key Specifications Number of Flip-Flops 2 (dual, independent) Supply Voltage Range 3V to 15V Toggle Frequency 10MHz typical at 10V, 4MHz at 5V Clock […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7847","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual D flip-flop, 3-15V CMOS, async S\/R, 10MHz toggle, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch)","in_stock":8500,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/cd4013b.pdf","price":"$0.55 @ 1ku","product_introduction":"The CD4013BE is a dual D-type flip-flop from Texas Instruments in the 4000B CMOS logic family. Each flip-flop has independent data (D), clock (CL), set (S), and reset (R) inputs, and complementary outputs (Q and Q-bar). Data on the D input is transferred to the Q output on the positive-going edge of the clock pulse. The set and reset inputs are asynchronous and active-high, overriding the clocked operation when asserted. The device operates over a wide 3V to 15V supply range with very low 2\u00b5A quiescent current, making it suitable for battery-powered and industrial applications. The military temperature range (-55\u00b0C to +125\u00b0C) ensures reliable operation in harsh environments.","working_principle":"The CD4013BE implements two independent edge-triggered D-type flip-flops using CMOS transmission gates and inverters. Each flip-flop consists of a master-slave latch configuration controlled by the clock signal. When the clock is low, the master latch is transparent (accepts D input) and the slave latch is isolated (holds previous Q). On the rising clock edge, the master latch becomes isolated (capturing D) and the slave latch becomes transparent (transferring master state to Q). This master-slave arrangement ensures that data is captured on the rising edge and held stable through the clock cycle. The asynchronous set input forces Q high and Q-bar low regardless of the clock and D inputs, while the reset input forces Q low and Q-bar high. When both S and R are asserted simultaneously, both Q and Q-bar go high (invalid state), and the final output state when both are released is indeterminate. The CMOS transmission gates use complementary NMOS\/PMOS pairs that pass the full logic swing, enabling rail-to-rail output levels.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>Q1<\/td>Output<\/td>Flip-flop 1 true output<\/td><\/tr>\n
      2<\/td>Q1-bar<\/td>Output<\/td>Flip-flop 1 complement output<\/td><\/tr>\n
      3<\/td>CL1<\/td>Input<\/td>Flip-flop 1 clock (rising edge triggered)<\/td><\/tr>\n
      4<\/td>R1<\/td>Input<\/td>Flip-flop 1 reset (active high, asynchronous)<\/td><\/tr>\n
      5<\/td>D1<\/td>Input<\/td>Flip-flop 1 data input<\/td><\/tr>\n
      6<\/td>S1<\/td>Input<\/td>Flip-flop 1 set (active high, asynchronous)<\/td><\/tr>\n
      7<\/td>VSS<\/td>Power<\/td>Ground (0V)<\/td><\/tr>\n
      8<\/td>S2<\/td>Input<\/td>Flip-flop 2 set (active high, asynchronous)<\/td><\/tr>\n
      9<\/td>D2<\/td>Input<\/td>Flip-flop 2 data input<\/td><\/tr>\n
      10<\/td>R2<\/td>Input<\/td>Flip-flop 2 reset (active high, asynchronous)<\/td><\/tr>\n
      11<\/td>CL2<\/td>Input<\/td>Flip-flop 2 clock (rising edge triggered)<\/td><\/tr>\n
      12<\/td>Q2-bar<\/td>Output<\/td>Flip-flop 2 complement output<\/td><\/tr>\n
      13<\/td>Q2<\/td>Output<\/td>Flip-flop 2 true output<\/td><\/tr>\n
      14<\/td>VDD<\/td>Power<\/td>Supply voltage (3V-15V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Frequency Division:<\/strong> Connect Q-bar to D to form a toggle flip-flop that divides the clock frequency by 2<\/li>\n
      • Shift Registers:<\/strong> Cascade D flip-flops by connecting Q to the next D input for serial data storage and transfer<\/li>\n
      • Debouncing:<\/strong> D input connected to VDD with a clocked push-button creates a clean, debounced toggle output<\/li>\n
      • Control Sequencing:<\/strong> Set and reset inputs provide asynchronous control for state machine initialization and override<\/li>\n
      • Data Synchronization:<\/strong> Captures asynchronous input data on clock edge for synchronous processing in digital systems<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Voltage<\/th><\/tr>\n
        CD4013BM<\/td>TI<\/td>SOIC-14 surface-mount version with identical dual D-type flip-flop functionality<\/td>SOIC-14<\/td>3-18V<\/td><\/tr>\n
        HEF4013BT<\/td>NXP<\/td>Pin-compatible CMOS version with wide 3-15V supply and improved ESD protection<\/td>SOIC-14<\/td>3-15V<\/td><\/tr>\n
        MC14013BDR2G<\/td>onsemi<\/td>Pin-compatible equivalent with automotive AEC-Q100 qualified variant available<\/td>SOIC-14<\/td>3-18V<\/td><\/tr>\n
        74HC74D<\/td>NXP<\/td>HC CMOS dual D-FF with higher speed (50MHz typ) and 2-6V supply range<\/td>SOIC-14<\/td>2-6V<\/td><\/tr>\n
        SN74LVC2G74DCUR<\/td>TI<\/td>Single D-FF in tiny VSSOP-8, 1.65-5.5V for low-voltage logic systems<\/td>VSSOP-8<\/td>1.65-5.5V<\/td><\/tr>\n
        74AUP2G74GWH<\/td>Nexperia<\/td>Ultra-low power dual D-FF with 0.8-3.6V supply for battery-powered designs<\/td>XSON-10<\/td>0.8-3.6V<\/td><\/tr>\n<\/table>\n

        CD4013BE is the industry-standard CMOS dual D-type flip-flop with independent Set, Reset, Clock, and Data inputs. HC74 versions offer higher speed at the cost of narrower voltage range. For modern low-voltage designs, LVC2G74 operates down to 1.65V.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7847","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7847"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7847\/revisions"}],"predecessor-version":[{"id":8119,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7847\/revisions\/8119"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7847"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7847"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7847"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7847"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}