{"id":7825,"date":"2026-06-27T04:11:45","date_gmt":"2026-06-27T04:11:45","guid":{"rendered":"https:\/\/materialparts.com\/at25sf128a-shb-t\/"},"modified":"2026-06-27T04:11:45","modified_gmt":"2026-06-27T04:11:45","slug":"at25sf128a-shb-t","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/at25sf128a-shb-t\/","title":{"rendered":"AT25SF128A-SHB-T"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The AT25SF128A-SHB-T is a 128Mbit (16MB) Serial NOR Flash Memory manufactured by Renesas Electronics (originally developed by Adesto Technologies). It features a Serial Peripheral Interface (SPI) compatible bus supporting standard, dual, and quad I\/O modes with clock frequencies up to 133 MHz. Housed in an industry-standard 8-lead wide-body SOIC package (0.209″ \/ 5.30mm width), this device is optimized for code storage and data logging applications in consumer electronics, IoT devices, and embedded systems, offering flexible erase architecture, low power consumption, and high reliability with 100K program\/erase cycles and 20-year data retention.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Parameter<\/strong><\/td>\nValue<\/strong><\/td>\n<\/tr>\n
\u5236\u9020\u5546<\/td>\nRenesas Electronics (Adesto Technologies)<\/td>\n<\/tr>\n
Memory Type<\/td>\nNon-Volatile NOR Flash<\/td>\n<\/tr>\n
Memory Size<\/td>\n128Mbit (16M x 8 \/ 16MB)<\/td>\n<\/tr>\n
Interface<\/td>\nSPI (Standard, Dual I\/O, Quad I\/O)<\/td>\n<\/tr>\n
Maximum Clock Frequency<\/td>\n133 \u5146\u8d6b<\/td>\n<\/tr>\n
Data Transfer Rate (Quad I\/O)<\/td>\nUp to 480 Mbps<\/td>\n<\/tr>\n
Data Transfer Rate (Quad Output)<\/td>\nUp to 532 Mbps<\/td>\n<\/tr>\n
Supply Voltage (VCC<\/sub>)<\/td>\n2.7V \u81f3 3.6V<\/td>\n<\/tr>\n
Active Supply Current<\/td>\n22 mA (max)<\/td>\n<\/tr>\n
Standby Current<\/td>\n13 µA (typ)<\/td>\n<\/tr>\n
Deep Power-Down Current<\/td>\n2 µA (typ)<\/td>\n<\/tr>\n
Access Time<\/td>\n7 ns<\/td>\n<\/tr>\n
Page Program Size<\/td>\n256 Bytes<\/td>\n<\/tr>\n
Page Program Time<\/td>\n0.6 ms (typ)<\/td>\n<\/tr>\n
Sector Erase (4 KB)<\/td>\n70 ms (typ)<\/td>\n<\/tr>\n
Block Erase (32 KB)<\/td>\n150 ms (typ)<\/td>\n<\/tr>\n
Block Erase (64 KB)<\/td>\n250 ms (typ)<\/td>\n<\/tr>\n
Full Chip Erase<\/td>\n30 s (typ)<\/td>\n<\/tr>\n
Endurance<\/td>\n100,000 program\/erase cycles<\/td>\n<\/tr>\n
Data Retention<\/td>\n20 years<\/td>\n<\/tr>\n
Security Registers<\/td>\n3 x 256-byte OTP<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\n8-SOIC Wide (0.209″ \/ 5.30mm width)<\/td>\n<\/tr>\n
\u5b89\u88c5\u7c7b\u578b<\/td>\nSurface Mount (SMT)<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n-40°C to +85°C (Industrial)<\/td>\n<\/tr>\n
Packing<\/td>\nTape & Reel<\/td>\n<\/tr>\n
RoHS Compliance<\/td>\nYes (ROHS3, Pb\/Halide-free)<\/td>\n<\/tr>\n
MSL \u7b49\u7ea7<\/td>\nMSL 1 (Unlimited)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • Flexible SPI Interface:<\/strong> Supports SPI Modes 0 and 3 with standard single-bit, dual I\/O (up to 240 Mbps), and quad I\/O (up to 480 Mbps) data transfer modes, enabling designers to balance pin count and throughput.<\/li>\n
  • High-Speed Performance:<\/strong> 133 MHz maximum clock frequency with 7 ns access time. Quad Output read achieves up to 532 Mbps throughput for rapid code fetch and data streaming.<\/li>\n
  • Optimized Erase Architecture:<\/strong> Flexible sector\/block erase options (4 KB sector, 32 KB block, 64 KB block) plus full chip erase accommodate both code storage and data logging use cases without wasting erase cycles.<\/li>\n
  • Low Power Consumption:<\/strong> Only 13 µA standby current and 2 µA deep power-down current make it ideal for battery-powered and energy-harvesting applications.<\/li>\n
  • Program\/Erase Suspend & Resume:<\/strong> Allows the system to pause an ongoing program or erase operation to perform a time-critical read, then resume without losing progress.<\/li>\n
  • Hardware & Software Write Protection:<\/strong> WP pin provides hardware-controlled locking of protected sectors; software block protection with top\/bottom selection via status register; three 256-byte OTP security registers for key storage.<\/li>\n
  • Serial Flash Discoverable Parameters (SFDP):<\/strong> Standardized parameter table enables automatic host controller configuration without hardcoded device-specific parameters.<\/li>\n
  • Continuous Read with Wrap:<\/strong> Supports 8\/16\/32\/64-byte wrap for cache-line-aligned execution, reducing overhead in XIP (Execute-in-Place) applications.<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Code Storage & Execute-in-Place (XIP):<\/strong> Stores firmware, bootloader, and application code for microcontrollers and application processors. The fast read speed and continuous read with wrap enable direct code execution from flash without copying to RAM, reducing boot time and memory footprint.<\/li>\n
    • IoT & Wearable Devices:<\/strong> Ideal for sensor data logging, configuration storage, and wireless firmware update (OTA) image buffering in smart home devices, wearables, and industrial IoT nodes where low standby current extends battery life.<\/li>\n
    • \u6d88\u8d39\u7535\u5b50\u4ea7\u54c1\uff1a<\/strong> Used in smart speakers, set-top boxes, TVs, and audio equipment for storing system firmware, UI assets, voice prompts, and user settings. The flexible erase architecture supports both large firmware images and frequent small data updates.<\/li>\n
    • Automotive & Industrial Data Logging:<\/strong> Records operational parameters, fault codes, and diagnostic data in automotive ECUs, PLCs, and industrial control systems. Wide industrial temperature range (-40°C to +85°C) ensures reliable operation in harsh environments.<\/li>\n
    • Communication Equipment:<\/strong> Stores FPGA bitstreams, routing tables, and configuration data in network switches, routers, base stations, and communication modules where fast boot and non-volatile storage are essential.<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The AT25SF128A-SHB-T is a 128Mbit (16MB) Serial NOR Flash Memory manufactured by Renesas Electronics (originally developed by Adesto Technologies). It features a Serial Peripheral Interface (SPI) compatible bus supporting standard, dual, and quad I\/O modes with clock frequencies up to 133 MHz. Housed in an industry-standard 8-lead wide-body SOIC package (0.209″ \/ 5.30mm […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[],"chip_brand":[12],"class_list":["post-7825","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","chip_brand-renesas"],"acf":{"brief_explanation":"128Mbit SPI NOR Flash, 133MHz, Quad I\/O, 2.7-3.6V, SOIC-8W, 100K cycles, 20yr retention","date_code":"","package_case":"8-SOIC Wide (0.209 inch \/ 5.30mm width, 5.0 x 5.3 x 2.16 mm)","in_stock":5364,"datasheet":"https:\/\/www.renesas.com\/en\/document\/dst\/at25sf128a-datasheet","price":"$1.71 @ 2ku","product_introduction":"The AT25SF128A-SHB-T is a 128Mbit (16MB) Serial NOR Flash Memory from Renesas Electronics (originally developed by Adesto Technologies \/ Dialog Semiconductor). Designed for high-volume consumer and industrial applications, this device provides flexible code storage and data logging capabilities through its SPI-compatible interface with support for standard, dual, and quad I\/O modes.\n\nWith a maximum clock frequency of 133 MHz and access time of just 7 ns, the AT25SF128A delivers fast read performance suitable for Execute-in-Place (XIP) applications. The quad I\/O interface achves data transfer rates up to 480 Mbps, while quad output mode pushes throughput to 532 Mbps, enabling rapid firmware fetch and data streaming.\n\nThe device features an optimized and flexible erase architecture that supports 4 KB sector erase, 32 KB and 64 KB block erase, and full chip erase. This granularity allows efficient use of flash space for both large firmware images and frequent small data updates, without wasting erase cycles on unused capacity. Program\/Erase suspend and resume capability further enhances system responsiveness.\n\nPower efficiency is a key strength: with only 13 uA standby current and 2 uA deep power-down current, the AT25SF128A-SHB-T is ideal for battery-powered and energy-harvesting designs. The device offers 100,000 program\/erase cycles and 20-year data retention, ensuring long-term reliability across industrial temperature range (-40C to +85C). Housed in a standard 8-lead wide-body SOIC package (0.209 inch \/ 5.30mm width), it is compatible with industry-standard PCB footprints.","working_principle":"

      NOR Flash Memory Architecture<\/h3>

      The AT25SF128A uses a NOR-type flash memory array where each memory cell consists of a single floating-gate MOS transistor. Unlike NAND flash, NOR architecture allows random access to individual bytes, making it suitable for code execution directly from the flash array (Execute-in-Place). The 128Mbit array is organized as 16M x 8 bits, addressable through 24-bit addressing.<\/p>

      SPI Interface Protocol<\/h3>

      Communication with the host controller occurs through a standard 4-wire SPI bus (CS, SCLK, SI\/MOSI, SO\/MISO). The device supports SPI Modes 0 and 3, with data latched on the rising edge of SCLK and output on the falling edge. Instructions are initiated by driving CS low, followed by an 8-bit instruction opcode. In standard mode, data transfers use single-bit serial communication. In dual and quad modes, the SI and SO pins (plus WP and HOLD pins in quad mode) become bidirectional I\/O lines, transferring 2 or 4 bits per clock cycle respectively.<\/p>

      Programming and Erase Mechanism<\/h3>

      Writing data involves a two-step process: first, the target area must be erased (flash cells return to logic high \/ 0xFF state), then individual bytes are programmed to the desired values. The device supports page programming of up to 256 bytes in a single operation (typical 0.6 ms). Erase operations are available at sector (4 KB), block (32 KB or 64 KB), or full chip level. Both program and erase operations can be suspended to allow time-critical read operations, then resumed.<\/p>

      Protection and Security<\/h3>

      The device provides multiple layers of write protection: hardware WP pin for sector-level locking, software block protection via status register with top\/bottom selection, and three 256-byte one-time programmable (OTP) security registers for storing encryption keys or unique identifiers. The Serial Flash Discoverable Parameters (SFDP) register enables automatic host controller configuration.<\/p>","pin_description":"
      Pin<\/th>Name<\/th>Type<\/th>Function<\/th><\/tr>
      1<\/td>CS (Chip Select)<\/td>Input<\/td>Active-low chip select; initiates instruction sequence when driven low; device enters standby when high; all inputs ignored and outputs high-Z when CS is high<\/td><\/tr>
      2<\/td>SO \/ IO1<\/td>I\/O<\/td>Serial data output in standard SPI mode; becomes bidirectional I\/O1 in dual and quad modes for data transfer<\/td><\/tr>
      3<\/td>WP \/ IO2<\/td>I\/O<\/td>Write protect input in standard\/dual mode; when low with SRP bits set, prevents status register writes; becomes bidirectional I\/O2 in quad mode; internal pull-up, may be left unconnected if not used<\/td><\/tr>
      4<\/td>GND<\/td>Power<\/td>Ground reference for all internal circuits and I\/O signals<\/td><\/tr>
      5<\/td>SI \/ IO0<\/td>I\/O<\/td>Serial data input in standard SPI mode; receives instructions, addresses, and program data; becomes bidirectional I\/O0 in dual and quad modes<\/td><\/tr>
      6<\/td>SCLK (Serial Clock)<\/td>Input<\/td>SPI clock input; latches input data on rising edge; output data changes on falling edge; provides synchronization reference for all SPI operations<\/td><\/tr>
      7<\/td>HOLD \/ IO3<\/td>I\/O<\/td>Hold (pause) control in standard\/dual mode; when CS is low and HOLD goes low, device suspends communication; becomes bidirectional I\/O3 in quad mode; internal pull-up, may be left unconnected if not used<\/td><\/tr>
      8<\/td>VCC<\/td>Power<\/td>Core and I\/O power supply (2.7V to 3.6V); requires 100nF decoupling capacitor placed close to pin<\/td><\/tr><\/table>

      Note: In Quad I\/O mode, pins 2 (IO1), 3 (IO2), 5 (IO0), and 7 (IO3) all function as bidirectional data lines, enabling 4-bit parallel data transfer per clock cycle.<\/em><\/p>","application_scenarios":"

      • Code Storage and Execute-in-Place (XIP):<\/strong> Stores firmware, bootloader, and application code for microcontrollers and application processors. The 133 MHz read speed and continuous read with 8\/16\/32\/64-byte wrap enable direct code execution from flash, reducing boot time and RAM requirements in resource-constrained embedded systems.<\/li>
      • IoT and Wearable Data Logging:<\/strong> Records sensor data, configuration parameters, and wireless OTA update images in smart home devices, wearables, and industrial IoT nodes. The 2 uA deep power-down current and 13 uA standby current maximize battery life in always-on sensing applications.<\/li>
      • Consumer Electronics Firmware:<\/strong> Used in smart speakers, set-top boxes, TVs, and audio equipment for storing system firmware, UI assets, voice prompts, and user preferences. The flexible 4 KB \/ 32 KB \/ 64 KB erase architecture supports both large firmware images and frequent small data updates.<\/li>
      • Automotive and Industrial Diagnostics:<\/strong> Records operational parameters, fault codes, and diagnostic data in automotive ECUs, PLCs, motor controllers, and industrial instrumentation. Industrial temperature range (-40C to +85C) ensures reliable operation in demanding environments.<\/li>
      • Communication Infrastructure:<\/strong> Stores FPGA bitstreams, routing tables, and boot configuration in network switches, routers, cellular base stations, and wireless access points where fast boot and reliable non-volatile storage are essential for network uptime.<\/li><\/ul>","alternative_models":"
        Manufacturer<\/th>Part Number<\/th>Package<\/th>Key Differences<\/th><\/tr>
        Winbond<\/td>W25Q128JVSIQ<\/td>SOIC-8W<\/td>Pin-compatible; 128Mbit SPI NOR; 133 MHz; wider voltage range (2.7-3.6V); industry-standard replacement<\/td><\/tr>
        Macronix<\/td>MX25L12833FZMI<\/td>SOIC-8W<\/td>128Mbit SPI NOR; 133 MHz; improved security features; MXICY branding<\/td><\/tr>
        GigaDevice<\/td>GD25Q128CSIG<\/td>SOIC-8W<\/td>128Mbit SPI NOR; 120 MHz; cost-effective alternative; compatible pinout<\/td><\/tr>
        Winbond<\/td>W25Q128FVSIQ<\/td>SOIC-8W<\/td>Older generation; 128Mbit; 104 MHz; proven track record; lower cost<\/td><\/tr>
        Micron<\/td>N25Q128A13ESF40F<\/td>SOIC-8W<\/td>128Mbit SPI NOR; 108 MHz; Micron\/Numonyx heritage; automotive qualified options<\/td><\/tr>
        Renesas (Adesto)<\/td>AT25SL128A-SHB-T<\/td>SOIC-8W<\/td>Same family; 128Mbit; enhanced low-voltage version (1.65-2.0V); pin-compatible<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7825","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7825"}],"version-history":[{"count":0,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7825\/revisions"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7825"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7825"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7825"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7825"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}