{"id":7805,"date":"2026-06-27T03:35:07","date_gmt":"2026-06-27T03:35:07","guid":{"rendered":"https:\/\/materialparts.com\/cy2304sxi-1t-2\/"},"modified":"2026-06-28T10:20:54","modified_gmt":"2026-06-28T10:20:54","slug":"cy2304sxi-1t-2","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/cy2304sxi-1t-2\/","title":{"rendered":"CY2304SXI-1T"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The CY2304SXI-1T is a 3.3V zero delay clock buffer from Infineon Technologies (formerly Cypress) with 4 outputs, on-chip PLL, 10-133 MHz operating range, and 90 ps typical jitter in an 8-pin SOIC package. The -1 configuration provides 1:1 output-to-reference frequency ratio.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\u7c7b\u578b<\/td>\nZero Delay Clock Buffer<\/td>\n<\/tr>\n
Number of Outputs<\/td>\n4 (2 banks of 2)<\/td>\n<\/tr>\n
\u914d\u7f6e<\/td>\n-1: All outputs = Reference frequency<\/td>\n<\/tr>\n
Operating Frequency<\/td>\n10 MHz to 133 MHz<\/td>\n<\/tr>\n
Input-Output Skew<\/td>\n< 250 ps<\/td>\n<\/tr>\n
Output-to-Output Skew<\/td>\n< 200 ps<\/td>\n<\/tr>\n
Cycle-to-Cycle Jitter<\/td>\n90 ps typical (66 MHz, 15 pF)<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n3.0 V to 3.6 V<\/td>\n<\/tr>\n
Supply Current<\/td>\n45 mA max (100 MHz, unloaded)<\/td>\n<\/tr>\n
Power-Down Current<\/td>\n25 \u00b5A max<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n-40\u00b0C to +85\u00b0C (Industrial)<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nSOIC-8 (150-mil)<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • Zero input-output propagation delay via on-chip PLL<\/li>\n
  • Adjustable delay via capacitive load on FBK pin<\/li>\n
  • Two banks of two low-skew outputs each<\/li>\n
  • 90 ps typical cycle-to-cycle jitter<\/li>\n
  • Power-down mode: outputs three-stated, PLL off, <25 \u00b5A<\/li>\n
  • Space-saving 8-pin SOIC package<\/li>\n
  • Multiple device synchronization (<500 ps device-to-device skew)<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • PC and workstation clock distribution<\/li>\n
    • Data communications equipment<\/li>\n
    • Telecom systems<\/li>\n
    • High-performance clock trees<\/li>\n
    • Embedded processor clocking<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The CY2304SXI-1T is a 3.3V zero delay clock buffer from Infineon Technologies (formerly Cypress) with 4 outputs, on-chip PLL, 10-133 MHz operating range, and 90 ps typical jitter in an 8-pin SOIC package. The -1 configuration provides 1:1 output-to-reference frequency ratio. Key Specifications Type Zero Delay Clock Buffer Number of Outputs 4 (2 […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[173],"class_list":["post-7805","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-infineon"],"acf":{"brief_explanation":"3.3V zero delay clock buffer, 4-out, PLL, 10-133MHz, 90ps jitter, SOIC-8","date_code":"","package_case":"SOIC-8 (150-mil, 3.9 x 4.9 mm)","in_stock":6234,"datasheet":"https:\/\/www.infineon.com\/dgdl\/CY2304.pdf","price":"$2.80 @ 1ku","product_introduction":"The CY2304SXI-1T is a 3.3V zero delay clock buffer from Infineon Technologies designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. It features an on-chip phase-locked loop (PLL) that locks to the input clock on the REF pin, with feedback driven into the FBK pin from one of the outputs. The input-to-output skew is guaranteed less than 250 ps, and output-to-output skew is guaranteed less than 200 ps. The -1T configuration provides all four outputs at the reference frequency with 1:1 ratio. The device enters power-down mode when no rising edges are detected on REF, three-stating all outputs and reducing current to below 25 \u00b5A.","working_principle":"The CY2304 uses an on-chip PLL to achieve zero input-to-output propagation delay. The PLL consists of a phase detector, loop filter, and voltage-controlled oscillator (VCO). The phase detector compares the REF input with the FBK feedback signal and adjusts the VCO to minimize phase error. The feedback path must be routed from one of the outputs back to the FBK pin, which effectively includes the output buffer delay in the PLL feedback loop. This means the PLL compensates for the output buffer propagation delay, achieving near-zero delay from REF to the outputs. The delay can be fine-tuned by adding capacitive loading on the FBK pin, which slightly increases the feedback path delay and correspondingly advances the output timing. Multiple CY2304 devices can be synchronized by driving them from the same REF clock, with device-to-device skew guaranteed below 500 ps.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>REF<\/td>Input<\/td>Reference clock input (LVCMOS\/LVTTL)<\/td><\/tr>\n
      2<\/td>CLKA1<\/td>Output<\/td>Bank A output 1<\/td><\/tr>\n
      3<\/td>CLKA2<\/td>Output<\/td>Bank A output 2<\/td><\/tr>\n
      4<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      5<\/td>CLKB1<\/td>Output<\/td>Bank B output 1<\/td><\/tr>\n
      6<\/td>CLKB2<\/td>Output<\/td>Bank B output 2<\/td><\/tr>\n
      7<\/td>FBK<\/td>Input<\/td>PLL feedback input (connect from CLKA1 or CLKB1)<\/td><\/tr>\n
      8<\/td>VDD<\/td>Power<\/td>Supply voltage (3.3V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • PC Clock Distribution:<\/strong> Zero delay buffer distributes motherboard clocks to CPU, chipset, and memory with minimal skew<\/li>\n
      • Datacom Equipment:<\/strong> 90 ps jitter performance ensures timing margins in high-speed networking clock trees<\/li>\n
      • Multi-Board Systems:<\/strong> Device-to-device skew below 500 ps enables synchronized clocking across multiple boards<\/li>\n
      • Processor Clocking:<\/strong> Low-skew 4-output buffer provides synchronous clocks to multi-core processors and peripherals<\/li>\n
      • Power-Managed Systems:<\/strong> Automatic power-down when REF clock stops reduces standby power to below 25 \u00b5A<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Specs<\/th><\/tr>\n
        CY2304SXI-2T<\/td>Infineon<\/td>Configurable \u00f72\/\u00d72 output frequencies<\/td>-<\/td>-<\/td><\/tr>\n
        CY2305SC-1<\/td>Infineon<\/td>Single bank, 5 outputs, commercial temp<\/td>-<\/td>-<\/td><\/tr>\n
        PI49FCT3807QE<\/td>Diodes Inc<\/td>1:10 clock buffer, similar function<\/td>-<\/td>-<\/td><\/tr>\n
        ICS557-03<\/td>Renesas<\/td>Zero delay buffer with 6 outputs<\/td>-<\/td>-<\/td><\/tr>\n
        NB3N5573<\/td>onsemi<\/td>3.3V zero delay buffer, 5 outputs<\/td>-<\/td>-<\/td><\/tr>\n<\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7805","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=7805"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7805\/revisions"}],"predecessor-version":[{"id":8322,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/7805\/revisions\/8322"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=7805"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=7805"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=7805"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=7805"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}