The TLC548CP from TI is an 8-bit 45.5kHz A\/D converter with serial I\/O interface and on-chip sample-and-hold in DIP-8 through-hole for simple analog-to-digital conversion.<\/p>\n
| \u5305\u88c5<\/td>\n | DIP-8 (300mil)<\/td>\n<\/tr>\n<\/table>\n\u7279\u70b9<\/h2>\n\u5e94\u7528<\/h2>\nProduct Overview The TLC548CP from TI is an 8-bit 45.5kHz A\/D converter with serial I\/O interface and on-chip sample-and-hold in DIP-8 through-hole for simple analog-to-digital conversion. Key Specifications Package DIP-8 (300mil) Features See datasheet for complete specifications Industry-standard package Applications Industrial control Consumer electronics Communication equipment Power management<\/p>","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[19,13],"tags":[],"chip_brand":[138],"class_list":["post-5716","post","type-post","status-publish","format-standard","hentry","category-analog-linear-ics","category-integrated-circuits-ics","chip_brand-ti"],"acf":{"brief_explanation":"8-bit A\/D converter, 45.5kHz, serial I\/O, DIP-8","date_code":"","package_case":"DIP-8 (300mil)","in_stock":12420,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/tlc548.pdf","price":"$1.50 @ 1ku","product_introduction":"The TLC548CP from TI is an 8-bit 45.5kHz A\/D converter with serial I\/O interface and on-chip sample-and-hold in DIP-8 through-hole for simple analog-to-digital conversion.","working_principle":"The TLC548CP is an 8-bit successive approximation register (SAR) analog-to-digital converter from Texas Instruments in DIP-8, with 45.5kHz sampling rate and serial I\/O interface. The conversion uses a capacitive DAC and comparator in a charge-redistribution architecture. A conversion begins when CS goes LOW: the previous result is shifted out on DATA OUT (MSB first) synchronized to I\/O CLOCK, while the new analog input is sampled. After 8 clock cycles, the new conversion result is available. The sampling rate of 45.5kHz corresponds to a 22us total cycle time (8 clocks + internal conversion). The reference voltage inputs (REF+ and REF-) define the full-scale range: the digital output code 255 corresponds to ANALOG IN = REF+ - 1 LSB. With REF+ = 5.000V and REF- = 0V, 1 LSB = 5V\/256 = 19.5mV. The analog input bandwidth extends to approximately 500kHz, but aliasing requires an anti-aliasing filter for signals above half the sample rate (22.75kHz). The input impedance is approximately 1GOhm (CMOS sample-and-hold), presenting minimal loading to the source. The differential nonlinearity (DNL) is +\/-0.5 LSB typical, guaranteeing no missing codes. The total unadjusted error is +\/-0.5 LSB. The device includes an on-chip system clock that controls the SAR conversion timing independently of I\/O CLOCK. The CP suffix specifies DIP-8, commercial temperature (0C to +70C). The device is designed for simple 3-wire microcontroller interfaces where SPI is not available.","pin_description":"
|