{"id":5446,"date":"2026-06-10T02:08:01","date_gmt":"2026-06-10T02:08:01","guid":{"rendered":"https:\/\/materialparts.com\/is61lv25616al-10tli\/"},"modified":"2026-06-10T02:08:01","modified_gmt":"2026-06-10T02:08:01","slug":"is61lv25616al-10tli","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/is61lv25616al-10tli\/","title":{"rendered":"IS61LV25616AL-10TLI"},"content":{"rendered":"<h2>\u4ea7\u54c1\u6982\u89c8<\/h2>\n<p>The IS61LV25616AL-10TLI from ISSI (Integrated Silicon Solution) is a 4Mbit (256K x 16-bit) high-speed asynchronous CMOS static RAM with 10ns access time in a 44-pin TSOP-II package. Operating at 3.3V with low power consumption, it provides fast scratchpad memory for embedded processors and industrial systems.<\/p>\n<h2>\u4e3b\u8981\u89c4\u683c<\/h2>\n<table>\n<tr>\n<td>Organization<\/td>\n<td>256K x 16 bits (4 Mbit)<\/td>\n<\/tr>\n<tr>\n<td>Access Time<\/td>\n<td>10 ns<\/td>\n<\/tr>\n<tr>\n<td>\u7535\u6e90\u7535\u538b<\/td>\n<td>3.135V to 3.6V (3.3V nominal)<\/td>\n<\/tr>\n<tr>\n<td>Active Power<\/td>\n<td>150 mW typical<\/td>\n<\/tr>\n<tr>\n<td>Standby Power<\/td>\n<td>10 mW typical (CMOS inputs)<\/td>\n<\/tr>\n<tr>\n<td>Active Current<\/td>\n<td>110 mA max<\/td>\n<\/tr>\n<tr>\n<td>Interface<\/td>\n<td>Parallel asynchronous<\/td>\n<\/tr>\n<tr>\n<td>Byte Control<\/td>\n<td>UB (upper) and LB (lower) byte<\/td>\n<\/tr>\n<tr>\n<td>Data Retention<\/td>\n<td>2.0V minimum<\/td>\n<\/tr>\n<tr>\n<td>\u5de5\u4f5c\u6e29\u5ea6<\/td>\n<td>-40 to +85 C (Industrial)<\/td>\n<\/tr>\n<tr>\n<td>\u5305\u88c5<\/td>\n<td>TSOP-II 44-pin (18.52 x 10.29 mm)<\/td>\n<\/tr>\n<\/table>\n<h2>\u7279\u70b9<\/h2>\n<ul>\n<li>10ns high-speed access time<\/li>\n<li>3.3V low-voltage operation<\/li>\n<li>Fully static operation (no clock\/refresh)<\/li>\n<li>Upper and lower byte control (UB\/LB)<\/li>\n<li>Chip enable (CE) and output enable (OE)<\/li>\n<li>Low active power: 150mW typical<\/li>\n<li>Data retention at 2.0V<\/li>\n<li>Industrial temperature range<\/li>\n<\/ul>\n<h2>\u5e94\u7528<\/h2>\n<ul>\n<li>CPU cache memory<\/li>\n<li>Embedded processor scratchpad<\/li>\n<li>Industrial control buffering<\/li>\n<li>Network switch forwarding table<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p>Product Overview The IS61LV25616AL-10TLI from ISSI (Integrated Silicon Solution) is a 4Mbit (256K x 16-bit) high-speed asynchronous CMOS static RAM with 10ns access time in a 44-pin TSOP-II package. Operating at 3.3V with low power consumption, it provides fast scratchpad memory for embedded processors and industrial systems. Key Specifications Organization 256K x 16 bits (4 [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[210],"class_list":["post-5446","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-issi"],"acf":{"brief_explanation":"4Mbit (256Kx16) async SRAM, 10ns, 3.3V, TSOP-44 industrial","date_code":"","package_case":"TSOP-II 44-pin (18.52 x 10.29 x 1.05 mm)","in_stock":18226,"datasheet":"https:\/\/www.issi.com\/WW\/pdf\/61-64C25616AL-AS.pdf","price":"$3.50 @ 1ku","product_introduction":"The IS61LV25616AL-10TLI from ISSI is a 4Mbit (256K x 16-bit) high-speed asynchronous CMOS static RAM in a 44-pin TSOP-II package. The LV suffix denotes 3.3V low-voltage operation, AL denotes the high-speed low-power variant, 10 indicates 10ns access time, TL denotes TSOP-II package, and I denotes industrial temperature range (-40 to +85C). The device uses ISSI's high-performance CMOS technology to achieve 10ns access time with only 150mW typical active power consumption. The 16-bit data bus with upper byte (UB) and lower byte (LB) enables supports byte-wise or word-wise access. Fully static operation requires no clock or refresh, simplifying system design. Chip enable (CE) and output enable (OE) inputs facilitate memory expansion. The device enters low-power standby mode when CE is deasserted with CMOS input levels, reducing power to 10mW typical.","working_principle":"The IS61LV25616AL operates as a standard asynchronous SRAM: (1) Read Cycle: The address is presented on A0-A17, CE and OE are asserted low, and UB\/LB select the byte(s). After the access time (10ns), data appears on I\/O0-I\/O15. No clock is required; the operation is fully static. (2) Write Cycle: The address is presented, CE and WE are asserted low, and UB\/LB select the byte(s). Data on the I\/O pins is written into the selected location. Write can be controlled by CE, WE, or UB\/LB signals. (3) Standby: When CE is high, the device enters standby mode. With CMOS input levels (VIN at VDD or VSS), standby power drops to 10mW typical. Data is retained as long as VDD is above 2.0V. (4) Byte Control: The UB and LB pins independently enable the upper byte (I\/O8-I\/O15) and lower byte (I\/O0-I\/O7), allowing byte-wise operations on the 16-bit bus. Both bytes can be accessed simultaneously for word operations.","pin_description":"<table><tr><th>Pin Group<\/th><th>Count<\/th><th>Type<\/th><th>Description<\/th><\/tr><tr><td>A0-A17<\/td><td>18<\/td><td>Input<\/td><td>Address inputs<\/td><\/tr><tr><td>I\/O0-I\/O15<\/td><td>16<\/td><td>I\/O<\/td><td>Data bus (bidirectional)<\/td><\/tr><tr><td>CE<\/td><td>1<\/td><td>Input<\/td><td>Chip enable (active low)<\/td><\/tr><tr><td>OE<\/td><td>1<\/td><td>Input<\/td><td>Output enable (active low)<\/td><\/tr><tr><td>WE<\/td><td>1<\/td><td>Input<\/td><td>Write enable (active low)<\/td><\/tr><tr><td>UB<\/td><td>1<\/td><td>Input<\/td><td>Upper byte enable (active low)<\/td><\/tr><tr><td>LB<\/td><td>1<\/td><td>Input<\/td><td>Lower byte enable (active low)<\/td><\/tr><tr><td>VDD\/VSS<\/td><td>5<\/td><td>Power<\/td><td>3.3V supply and ground<\/td><\/tr><\/table>","application_scenarios":"<ul><li>Embedded processor scratchpad RAM with 10ns access, 16-bit bus, and 3.3V supply<\/li><li>Industrial PLC data buffer with byte-wise access via UB\/LB and 4Mbit capacity<\/li><li>Network switch forwarding table with 150mW low active power and CE-based power management<\/td><li>Battery-backed SRAM with 2.0V data retention and 10mW CMOS standby power<\/li><\/ul>","alternative_models":"<table><tr><th>Model<\/th><th>Manufacturer<\/th><th>Size<\/th><th>Speed<\/th><th>Notes<\/th><\/tr><tr><td>CY62167EV30LL-55ZXI<\/td><td>Infineon<\/td><td>4Mbit<\/td><td>55ns<\/td><td>Very low power<\/td><\/tr><tr><td>AS6C1616-55TIN<\/td><td>Alliance<\/td><td>4Mbit<\/td><td>55ns<\/td><td>Lower speed alternative<\/td><\/tr><tr><td>IS61WV25616BLL-10TLI<\/td><td>ISSI<\/td><td>4Mbit<\/td><td>10ns<\/td><td>Very low power version<\/td><\/tr><tr><td>HM62V1616ILTT-10<\/td><td>Renesas<\/td><td>4Mbit<\/td><td>10ns<\/td><td>Pin-compatible<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/5446","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=5446"}],"version-history":[{"count":0,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/5446\/revisions"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=5446"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=5446"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=5446"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=5446"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}