{"id":3015,"date":"2026-05-29T04:39:02","date_gmt":"2026-05-29T04:39:02","guid":{"rendered":"https:\/\/materialparts.com\/sn74hc273nsr\/"},"modified":"2026-05-29T06:56:32","modified_gmt":"2026-05-29T06:56:32","slug":"sn74hc273nsr","status":"publish","type":"post","link":"https:\/\/materialparts.com\/zh\/sn74hc273nsr\/","title":{"rendered":"SN74HC273NSR"},"content":{"rendered":"

\u4ea7\u54c1\u6982\u89c8<\/h2>\n

The Texas Instruments SN74HC273NSR is an octal positive-edge-triggered D-type flip-flop with an active-low clear input, packaged in a 20-pin SOP (NS). Each of the eight flip-flops has an individual data input and a single-rail output, sharing a common clock and asynchronous clear. With 2 V to 6 V operation and 12 ns typical propagation delay, it is designed for data storage, address latching, and register applications.<\/p>\n

\u4e3b\u8981\u89c4\u683c<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\u529f\u80fd<\/td>\nOctal D-Type Flip-Flop with Clear<\/td>\n<\/tr>\n
\u6e20\u9053<\/td>\n8<\/td>\n<\/tr>\n
Trigger Type<\/td>\nPositive-edge triggered<\/td>\n<\/tr>\n
\u7535\u6e90\u7535\u538b<\/td>\n2 V ~ 6 V<\/td>\n<\/tr>\n
Propagation Delay (tpd)<\/td>\n12 ns typical<\/td>\n<\/tr>\n
Output Drive<\/td>\n\u00b14 mA at 5 V (IOL\/IOH: 5.2 mA \/ -5.2 mA max)<\/td>\n<\/tr>\n
ICC (max)<\/td>\n80 \u00b5A<\/td>\n<\/tr>\n
Max Clock Frequency<\/td>\n28 MHz<\/td>\n<\/tr>\n
Clear Input<\/td>\nActive-low (asynchronous)<\/td>\n<\/tr>\n
\u8f93\u5165\u7c7b\u578b<\/td>\n\u6807\u51c6 CMOS<\/td>\n<\/tr>\n
\u8f93\u51fa\u7c7b\u578b<\/td>\nPush-Pull<\/td>\n<\/tr>\n
\u5305\u88c5<\/td>\nSOP-20 (NS) (12.6\u00d77.8 mm)<\/td>\n<\/tr>\n
\u5de5\u4f5c\u6e29\u5ea6<\/td>\n-40\u00b0C ~ +85\u00b0C<\/td>\n<\/tr>\n<\/table>\n

\u7279\u70b9<\/h2>\n
    \n
  • Eight edge-triggered D-type flip-flops with single-rail outputs in a single package<\/li>\n
  • Asynchronous active-low clear (CLR) input resets all outputs independently of clock<\/li>\n
  • Individual data input for each flip-flop<\/li>\n
  • Wide operating voltage range: 2 V to 6 V<\/li>\n
  • Low power consumption: 80 \u00b5A max ICC<\/li>\n
  • Can drive up to 10 LSTTL loads<\/li>\n
  • Positive input clamp diodes for ESD protection<\/li>\n<\/ul>\n

    \u5e94\u7528<\/h2>\n
      \n
    • Data storage and address latching in microprocessor systems<\/li>\n
    • Output register for bus-oriented systems<\/li>\n
    • Parallel data hold and synchronization<\/li>\n
    • State machine and control logic registers<\/li>\n
    • Digital delay and pipeline register stages<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The Texas Instruments SN74HC273NSR is an octal positive-edge-triggered D-type flip-flop with an active-low clear input, packaged in a 20-pin SOP (NS). Each of the eight flip-flops has an individual data input and a single-rail output, sharing a common clock and asynchronous clear. With 2 V to 6 V operation and 12 ns typical […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[],"chip_brand":[138],"class_list":["post-3015","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","chip_brand-ti"],"acf":{"brief_explanation":"Octal D-type flip-flop, edge-triggered, async clear, 28MHz, SOP-20","date_code":"","package_case":"SOP-20 (NS) (12.6\u00d77.8 mm)","in_stock":8359,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74hc273.pdf","price":"$0.306 @ 1ku","product_introduction":"The SN74HC273NSR from Texas Instruments contains eight positive-edge-triggered D-type flip-flops with a direct active-low clear (CLR) input. Data at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either high or low level, the D input has no effect on the output. The asynchronous CLR input, when asserted LOW, overrides the clock and forces all Q outputs LOW regardless of the D input states. The device operates over a wide voltage range of 2 V to 6 V with typical propagation delay of 12 ns, making it suitable for a wide variety of data storage and register applications.","working_principle":"The SN74HC273NSR contains eight independent D-type flip-flops sharing common clock (CLK) and clear (CLR) signals. Each flip-flop consists of a master-slave latch structure controlled by the clock edge. On the rising edge of CLK, the data present at each D input is captured and transferred to the corresponding Q output. The setup time requirement specifies the minimum time that data must be stable before the clock edge; the hold time specifies the minimum time data must remain stable after the clock edge. The asynchronous CLR input, when driven LOW, forces all Q outputs LOW immediately, overriding any clock or data input activity. The output stages use push-pull (totem-pole) CMOS drivers capable of sourcing or sinking up to 5.2 mA while maintaining valid logic levels. The internal CMOS structure provides very low static power consumption of 80 \u00b5A maximum.","pin_description":"
      Pin<\/th>Name<\/th>Type<\/th>Function<\/th><\/tr>
      1<\/td>CLR<\/td>Input<\/td>Asynchronous clear (active low), resets all Q outputs<\/td><\/tr>
      2<\/td>Q1<\/td>Output<\/td>Flip-flop 1 output<\/td><\/tr>
      3<\/td>D1<\/td>Input<\/td>Flip-flop 1 data input<\/td><\/tr>
      4-11<\/td>D2-D5, Q2-Q5<\/td>I\/O<\/td>Flip-flops 2-5 data inputs and outputs<\/td><\/tr>
      12<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>
      13-18<\/td>D6-D8, Q6-Q8<\/td>I\/O<\/td>Flip-flops 6-8 data inputs and outputs<\/td><\/tr>
      19<\/td>CLK<\/td>Input<\/td>Common clock input (positive-edge triggered)<\/td><\/tr>
      20<\/td>VCC<\/td>Power<\/td>Supply voltage (2-6V)<\/td><\/tr><\/table>","application_scenarios":"
      • Address latching: Capturing and holding address data from a multiplexed address\/data bus in microprocessor systems<\/li>
      • Output registers: Holding output data stable in bus-oriented designs while the source changes<\/li>
      • Data synchronization: Capturing asynchronous input data on a clock edge to eliminate metastability<\/li>
      • State machines: Storing the current state vector in sequential logic designs<\/li>
      • Pipeline registers: Inter-stage data storage in digital signal processing pipelines<\/li><\/ul>","alternative_models":"
        Manufacturer<\/th>Part Number<\/th>Package<\/th>Notes<\/th><\/tr>
        TI<\/td>SN74HC273N<\/td>PDIP-20<\/td>Through-hole DIP package equivalent<\/td><\/tr>
        TI<\/td>SN74HC273PWR<\/td>TSSOP-20<\/td>Smaller surface-mount package<\/td><\/tr>
        TI<\/td>SN74HCT273NSR<\/td>SOP-20<\/td>HCT version, TTL-compatible inputs (4.5-5.5V)<\/td><\/tr>
        Nexperia<\/td>74HC273D<\/td>SOIC-20<\/td>Direct equivalent from Nexperia<\/td><\/tr>
        TI<\/td>SN74HC374N<\/td>PDIP-20<\/td>Similar but with 3-state outputs (OE instead of CLR)<\/td><\/tr>
        onsemi<\/td>MC74HC273ADWR2G<\/td>SOIC-20<\/td>Direct equivalent from onsemi<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/3015","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/comments?post=3015"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/3015\/revisions"}],"predecessor-version":[{"id":3030,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/posts\/3015\/revisions\/3030"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/media?parent=3015"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/categories?post=3015"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/tags?post=3015"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/zh\/wp-json\/wp\/v2\/chip_brand?post=3015"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}