Onsemi\uff08\u539f\u98de\u5146\u534a\u5bfc\u4f53\uff09\u7684 NC7SZ66P5X \u662f TinyLogic UHS \u7cfb\u5217\u7684\u5355\u5200\u5355\u63b7 (SPST) \u603b\u7ebf\u5f00\u5173\uff0c\u91c7\u7528 5 \u5f15\u811a SC-70 \u5c01\u88c5 (2.0 x 1.25 mm)\u3002\u5b83\u7684\u5de5\u4f5c\u7535\u538b\u4e3a 1.65 V \u81f3 5.5 V\uff0c\u5178\u578b\u5bfc\u901a\u7535\u963b\u4e3a 5 \u03a9\uff0c\u5177\u6709\u8f68\u81f3\u8f68\u4fe1\u53f7\u5904\u7406\u80fd\u529b\uff0c\u5728 5 V \u7535\u538b\u4e0b\u5177\u6709\u4e9a\u7eb3\u79d2\u7ea7\u4f20\u64ad\u5ef6\u8fdf\u3002\u5f00\u5173\u5728 OE \u4e3a\u9ad8\u7535\u5e73\u65f6\u542f\u7528\uff08\u5c06\u7aef\u53e3 A \u8fde\u63a5\u5230\u7aef\u53e3 B\uff09\uff0c\u5728 OE \u4e3a\u4f4e\u7535\u5e73\u65f6\u65ad\u5f00\u3002\u6389\u7535\u9ad8\u963b\u6297 I\/O \u53ef\u9632\u6b62\u56de\u6d41\u7535\u6d41\u3002\u5de5\u4f5c\u6e29\u5ea6\u8303\u56f4\u4e3a -40\u00b0C \u81f3 +85\u00b0C\u3002\u540e\u7f00 P5X \u8868\u793a 3000 \u4e2a SC-70 \u5377\u5e26\u3002.<\/p>","protected":false},"excerpt":{"rendered":"
The NC7SZ66P5X from onsemi (formerly Fairchild) is a single-pole\/single-throw (SPST) bus switch from the TinyLogic UHS family in a 5-pin SC-70 package (2.0 x 1.25 mm). It operates from 1.65 V to 5.5 V with 5 \u03a9 typical on-resistance, rail-to-rail signal handling, and sub-nanosecond propagation delay at 5 V. The switch is enabled when OE […]<\/p>\n","protected":false},"author":2,"featured_media":2887,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,15],"tags":[],"chip_brand":[144],"class_list":["post-2061","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-integrated-circuits-ics","category-logic-chips","chip_brand-on"],"acf":{"brief_explanation":"SPST bus switch, 1.65-5.5V, 5\u03a9 Ron, sub-ns delay, rail-to-rail, SC-70-5, OE active-high","date_code":"","package_case":"SC-70-5 \/ SOT-353 \/ SC-88A (2.0 x 1.25 x 1.0 mm, 0.65mm pitch)","in_stock":2290,"datasheet":"https:\/\/www.onsemi.com\/pub\/Collateral\/NC7SZ66-D.PDF","price":"$0.03 (3K+ pcs)","product_introduction":"The NC7SZ66 from onsemi's TinyLogic UHS family is a single-bit SPST bus switch in an ultra-small SC-70-5 package. The NC7SZ66P5X is the tape-and-reel version with 3000 units per reel. Originally designed by Fairchild Semiconductor (now part of onsemi), the device provides a low-impedance pass-through path between two ports with minimal propagation delay.\n\nWhen the output enable (OE) pin is HIGH, the switch closes and port A connects to port B through approximately 5 \u03a9. When OE is LOW, the switch opens and a high-impedance state exists between the two ports. The switch handles signals from 0 V to VCC (rail-to-rail), and the 5 \u03a9 on-resistance introduces negligible voltage drop for typical logic signals.\n\nThe key advantage of a bus switch over a buffer is zero propagation delay contribution other than the RC delay through the on-resistance and load capacitance. At 5 V, the propagation delay through the switch is typically 0.3 ns, making it essentially transparent to timing budgets.\n\nThe device supports over-voltage tolerant inputs up to 7 V, enabling voltage translation between different logic domains. When VCC is 0 V, all I\/O pins enter a high-impedance state, preventing backflow current in partially-powered systems \u2014 critical for hot-swap and power-sequencing applications.\n\nThe NC7SZ66 is available in three packages: SC-70-5 (P5X), SOT-23-5 (M5X), and MicroPak-6 (L6X). The SC-70-5 version occupies only 2.5 mm\u00b2 of board area.\n\nNote: Some distributors list the NC7SZ66P5X as obsolete, but it remains available from multiple sources. Verify current availability before designing into new products.","working_principle":"**CMOS Transmission Gate:** The NC7SZ66 uses a CMOS transmission gate (parallel NMOS + PMOS) as the switch element. The NMOS passes signals near VCC well, while the PMOS passes signals near GND well. Together, they provide rail-to-rail signal handling with a relatively flat on-resistance across the full voltage range. The typical 5 \u03a9 on-resistance is the parallel combination of both transistors.\n\n**OE Control Logic:** When OE is HIGH, both the NMOS and PMOS gates are driven to turn on their respective transistors, creating a low-impedance path between A and B. When OE is LOW, both transistors turn off, isolating the two ports with high impedance and low off-state leakage (< 1 nA typical).\n\n**Over-Voltage Tolerance:** Input and I\/O pins incorporate circuitry that tolerates voltages up to 7 V independently of VCC. When a voltage above VCC appears on a switch port, the internal ESD diode to VCC is reverse-biased, preventing current flow into the VCC rail.\n\n**Power-Off High-Impedance:** When VCC is 0 V, an internal circuit disables the switch and places all I\/O in high-impedance, preventing any current path between ports or into the supply. This enables hot-swap and live-insertion applications.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | OE<\/td> | I<\/td> | Output enable (active HIGH); HIGH = switch on (A connected to B); LOW = switch open (high-Z between A and B); 7V tolerant; CMOS input levels<\/td><\/tr> | ||||||||||||||||||||||||||||
| 2<\/td> | A<\/td> | I\/O<\/td> | Switch port A; bidirectional; 0 to VCC signal range; 5\u03a9 Ron to port B when enabled; 6pF I\/O capacitance; high-Z when disabled or powered down<\/td><\/tr> | ||||||||||||||||||||||||||||
| 3<\/td> | GND<\/td> | G<\/td> | Ground; connect to PCB ground plane<\/td><\/tr> | ||||||||||||||||||||||||||||
| 4<\/td> | B<\/td> | I\/O<\/td> | Switch port B; bidirectional; same characteristics as port A; signals pass through in either direction<\/td><\/tr> | ||||||||||||||||||||||||||||
| 5<\/td> | VCC<\/td> | P<\/td> | Supply voltage; 1.65V to 5.5V; bypass with 0.1\u00b5F ceramic to GND; switch signal range is 0 to VCC<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|