Microchip Technology\uff08\u524d\u8eab\u4e3a Atmel\uff09\u7684 ATSAMD20J17A-AU \u662f\u4e00\u6b3e\u57fa\u4e8e ARM Cortex-M0+ \u7684 32 \u4f4d\u5fae\u63a7\u5236\u5668\uff0c\u5177\u6709 128 KB \u95ea\u5b58\u548c 16 KB SRAM\uff0c\u91c7\u7528 64 \u5f15\u811a TQFP\uff0810 x 10 mm\uff09\u5c01\u88c5\uff0c\u5e26\u88f8\u9732\u710a\u76d8\u3002\u4e3b\u8981\u89c4\u683cARM Cortex-M0+ \u5185\u6838\uff0c\u9891\u7387\u9ad8\u8fbe 48 MHz\uff1b\u5355\u5468\u671f\u786c\u4ef6\u4e58\u6cd5\u5668\uff1b128 KB \u7cfb\u7edf\u5185\u53ef\u81ea\u52a8\u7f16\u7a0b\u95ea\u5b58\uff1b16 KB SRAM\uff1b2.46 CoreMark\/MHz\uff1b\u7535\u6e90\u7535\u538b 1.62 V \u81f3 3.63 V\uff1b\u4e0a\u7535\u590d\u4f4d (POR) \u548c\u6389\u7535\u68c0\u6d4b (BOD)\uff1b48 MHz \u6570\u5b57\u9501\u76f8\u73af (DFLL48M) \u548c 48-96 MHz \u5c0f\u6570\u6570\u5b57\u9501\u76f8\u73af (FDPLL96M)\uff1b\u5185\u90e8\u632f\u8361\u5668\uff1a32 kHz\u300132 kHz ULP\u30018 MHz\uff1b\u5916\u90e8\u6676\u4f53 32.768 kHz \u548c 0.4-32 MHz\uff1b\u5e26 16 \u4e2a\u5916\u90e8\u4e2d\u65ad\u548c\u4e00\u4e2a NMI \u7684\u5916\u90e8\u4e2d\u65ad\u63a7\u5236\u5668 (EIC)\uff1b8 \u901a\u9053\u4e8b\u4ef6\u7cfb\u7edf\uff1b6 \u4e2a\u4e32\u884c\u901a\u4fe1\u63a5\u53e3 (SERCOM)\uff0c\u6bcf\u4e2a\u63a5\u53e3\u53ef\u914d\u7f6e\u4e3a USART\uff08\u5168\u53cc\u5de5\u6216\u5355\u7ebf\u534a\u53cc\u5de5\uff09\u3001I2C\uff08\u6700\u9ad8 400 kHz\uff09\u6216 SPI\uff1b8 \u4e2a 16 \u4f4d\u5b9a\u65f6\u5668\/\u8ba1\u6570\u5668 (TC)\uff0c\u53ef\u914d\u7f6e\u4e3a 5 \u4e2a\u72ec\u7acb\u7684 16 \u4f4d TC \u6216\u5408\u5e76\u4e3a 32 \u4f4d TC\uff1b16 \u4e2a PWM \u901a\u9053\uff1b\u5e26\u65f6\u949f\/\u65e5\u5386\u7684 32 \u4f4d\u5b9e\u65f6\u8ba1\u6570\u5668 (RTC)\uff1b\u770b\u95e8\u72d7\u5b9a\u65f6\u5668 (WDT)\uff1bCRC-32 \u53d1\u751f\u5668\uff1b\u4e00\u4e2a 12 \u4f4d 350 ksps ADC\uff0c\u5e26 20 \u4e2a\u901a\u9053\uff08\u5dee\u5206\u548c\u5355\u7aef\u30011\/2 \u500d\u81f3 16 \u500d\u53ef\u7f16\u7a0b\u589e\u76ca\u3001\u81ea\u52a8\u504f\u79fb\u548c\u589e\u76ca\u8bef\u5dee\u8865\u507f\u3001\u8fc7\u91c7\u6837\u548c\u62bd\u53d6\uff0c\u6709\u6548\u5206\u8fa8\u7387\u4e3a 13-16 \u4f4d\uff09\uff1b\u4e00\u4e2a 10 \u4f4d 350 ksps DAC\uff1b\u4e24\u4e2a\u6a21\u62df\u6bd4\u8f83\u5668 (AC)\uff0c\u5e26\u7a97\u53e3\u6bd4\u8f83\u529f\u80fd\uff1b\u5916\u8bbe\u89e6\u6478\u63a7\u5236\u5668 (PTC)\uff0c\u5177\u6709 256 \u901a\u9053\u7535\u5bb9\u5f0f\u89e6\u6478\u548c\u63a5\u8fd1\u611f\u5e94\u529f\u80fd\uff1b52 \u4e2a GPIO \u5f15\u811a\uff1bSleepWalking \u5916\u56f4\u8bbe\u5907\uff1b\u7a7a\u95f2\u548c\u5f85\u673a\u7761\u7720\u6a21\u5f0f\uff1b\u529f\u8017\u5728\u6d3b\u52a8\u6a21\u5f0f\u4e0b\u4f4e\u81f3 70 uA\/MHz\uff0c\u89e6\u6478\u63a7\u5236\u5668\u8fd0\u884c\u65f6\u4e3a 8 uA\uff1bSWD \u8c03\u8bd5\u63a5\u53e3\uff1b\u5de5\u4f5c\u6e29\u5ea6\u4e3a -40 \u81f3 +85 \u6444\u6c0f\u5ea6\uff08A \u7ea7\uff09\u6216 -40 \u81f3 +105 \u6444\u6c0f\u5ea6\u3002\u7b26\u5408 RoHS3 \u6807\u51c6\u3002\u6fc0\u6d3b\/\u751f\u4ea7\u72b6\u6001\u3002.<\/p>","protected":false},"excerpt":{"rendered":"
The ATSAMD20J17A-AU from Microchip Technology (formerly Atmel) is an ARM Cortex-M0+ based 32-bit microcontroller featuring 128 KB Flash memory and 16 KB SRAM in a 64-pin TQFP (10 x 10 mm) package with exposed pad. Key specifications: ARM Cortex-M0+ core at up to 48 MHz; single-cycle hardware multiplier; 128 KB in-system self-programmable Flash; 16 KB […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[14,13],"tags":[],"chip_brand":[134],"class_list":["post-1990","post","type-post","status-publish","format-standard","hentry","category-clock-timing-ics","category-integrated-circuits-ics","chip_brand-microchip"],"acf":{"brief_explanation":"ARM Cortex-M0+ MCU 48MHz, 128KB Flash, 16KB SRAM, 6xSERCOM (I2C\/SPI\/UART), 12-bit ADC 20ch, 10-bit DAC, PTC touch, TQFP-64, -40~85C","date_code":"","package_case":"TQFP-64 EP (10 x 10 x 1.2 mm, 0.5mm pitch)","in_stock":12000,"datasheet":"https:\/\/www.microchip.com\/en-us\/product\/atsamd20j17","price":"$2.95 (1K+ pcs)","product_introduction":"The ATSAMD20J17A-AU from Microchip Technology is a member of the SAM D20 family of low-power ARM Cortex-M0+ microcontrollers. It represents the highest pin-count (64-pin J variant) with mid-density memory (128 KB Flash \/ 16 KB SRAM), providing the maximum peripheral count and I\/O availability in the SAM D20 family.\n\nThe SAM D20 family was originally developed by Atmel (acquired by Microchip in 2016) and is part of the SAM (Smart ARM-based Microcontroller) product line. The D20 is the base variant in the SAM D2x series, optimized for low power and general-purpose embedded applications. Other variants include the SAM D21 (with USB), SAM D10\/D11 (smaller pin-count, lower cost), and SAM DA1 (automotive qualified).\n\nThe key differentiator of the SAM D20 family is the SERCOM (Serial Communication Interface) peripheral. Each SERCOM can be independently configured as USART, I2C, or SPI, providing unparalleled flexibility in communication interface allocation. With six SERCOM modules, the ATSAMD20J17A-AU can simultaneously support up to six independent serial channels in any combination (e.g., 3x SPI, 2x I2C, 1x USART). This eliminates the common problem of running out of a specific interface type (e.g., needing 3 SPI ports but the MCU only has 2).\n\nThe 8-channel event system is another unique feature that allows peripherals to communicate directly without CPU intervention. For example, an external interrupt can trigger an ADC conversion, which when complete can trigger a DMA transfer, which can trigger a timer start. This event-driven architecture reduces interrupt latency and CPU overhead, and enables SleepWalking where peripherals operate autonomously while the CPU is in sleep mode.\n\nThe 12-bit ADC with 20 channels, programmable gain stage (1\/2x to 16x), and hardware oversampling (up to 16-bit effective resolution) is significantly more capable than typical M0+ MCU ADCs. The programmable gain stage eliminates the need for external signal conditioning amplifiers in many sensor applications. The differential input capability and automatic offset\/gain error compensation improve measurement accuracy. The hardware oversampling and decimation provide 13, 14, 15, or 16-bit effective resolution without CPU computation.\n\nThe 10-bit 350 ksps DAC is relatively uncommon in M0+ microcontrollers and enables analog output generation (waveforms, control voltages, audio) without external DAC components. Combined with the DMA controller and timer-triggered conversion, the DAC can generate complex waveforms autonomously.\n\nThe Peripheral Touch Controller (PTC) with 256-channel capacitive touch support is inherited from Microchip's mTouch technology and provides hardware-accelerated capacitive sensing for buttons, sliders, wheels, and proximity detection. The PTC can operate at only 8 uA in standby mode, continuously scanning touch sensors and waking the CPU only when a touch is detected. This ultra-low-power touch scanning is a key advantage for battery-powered consumer products.\n\nThe 52 GPIO pins provide extensive I\/O capability for the 64-pin package. All GPIO pins are individually configurable with peripheral multiplexing (up to 8 alternate functions per pin via the PORT MUX), interrupt capability (16 external interrupts through the EIC), and configurable pull-up\/pull-down resistors.\n\nThe ATSAMD20J17A-AU uses the A temperature grade (-40 to 85 degrees C). The same device is also available in the automotive-qualified and extended temperature variants. The AU suffix indicates the TQFP-64 package with tray packaging (the AUT suffix is tape and reel).\n\nDevelopment is supported by Microchip's MPLAB X IDE, MPLAB Harmony v3 framework, and Atmel Studio (legacy). The SAM D20 is also well-supported by Arduino (the Arduino Zero\/M0 uses the SAM D21, which shares the same architecture and peripherals), Zephyr RTOS, and ARM mbed OS (legacy).","working_principle":"The ATSAMD20J17A-AU operates as a complete 32-bit embedded microcontroller system on a single chip, integrating the ARM Cortex-M0+ processor core with Flash memory, SRAM, and a comprehensive set of flexible peripherals.\n\nARM Cortex-M0+ Core: The Cortex-M0+ is a 32-bit RISC processor implementing the ARMv6-M architecture with the Thumb instruction set. It features a 2-stage pipeline (fewer stages than the Cortex-M0 3-stage pipeline) for improved power efficiency. The M0+ includes a single-cycle hardware multiplier (32x32 to 32-bit result), a nested vectored interrupt controller (NVIC) with configurable priority levels, and a Micro Trace Buffer (MTB) for instruction trace. The core achieves 2.46 CoreMark\/MHz, providing approximately 118 CoreMark at 48 MHz.\n\nMemory System: The 128 KB Flash stores program code and constant data, organized as 512-byte pages for erase operations. The Flash supports in-system programming (ISP) via SWD and in-application programming (IAP) for firmware updates. The Flash wait states are automatically managed by the NVMCTRL based on the CPU frequency. The 16 KB SRAM is organized as a single bank with single-cycle access at 48 MHz. The SRAM is organized as two sections: the first 8 KB is bit-bandable and can be retained in standby mode, while the remaining 8 KB is not retained.\n\nClock System: The clock system is highly flexible with multiple sources. The internal 8 MHz RC oscillator (OSC8M) provides a default clock at startup. The DFLL48M (Digital Frequency Locked Loop) can multiply the 32 kHz reference to 48 MHz with high accuracy. The FDPLL96M (Fractional Digital Phase Locked Loop) can generate frequencies from 48 MHz to 96 MHz from various reference sources. External crystal oscillators (XOSC32K for 32.768 kHz RTC crystal, XOSC for 0.4-32 MHz main crystal) provide precise timing. The clock system supports dynamic clock switching and glitch-free frequency transitions.\n\nSERCOM Modules: Each of the six SERCOM modules is a universal serial communication peripheral that can be configured as USART, I2C, or SPI. The configuration is set through registers and can be changed at runtime (with proper de-initialization). Each SERCOM has its own interrupt, DMA trigger, and clock domain. The I2C mode supports Standard (100 kHz), Fast (400 kHz), and High-Speed modes. The SPI mode supports master and slave operation with configurable clock polarity and phase. The USART mode supports full-duplex, half-duplex, and LIN protocol with fractional baud rate generation.\n\nEvent System: The 8-channel event system connects event generators (timers, ADC, EIC, etc.) to event users (ADC triggers, DMA requests, timer actions, etc.) without CPU intervention. Events are transmitted in 1-2 clock cycles, much faster than interrupt-driven handling. The event system operates even in standby sleep mode, enabling SleepWalking peripherals. For example, the RTC can generate a periodic event that triggers the ADC to sample a sensor, and if the ADC result exceeds a threshold (via the analog comparator window function), the CPU is woken from standby.\n\nADC Operation: The 12-bit ADC supports single-ended and differential input modes. In differential mode, the positive and negative inputs can be any of the 20 ADC channels, providing maximum flexibility. The programmable gain stage (1\/2x to 16x) amplifies small signals before conversion, improving the effective resolution for low-amplitude sensors. The hardware oversampling accumulates 2^N samples and divides by 2^N to achieve N\/2 bits of additional resolution (e.g., 4x oversampling gives 13-bit effective resolution). The offset and gain error compensation automatically corrects systematic ADC errors using factory-calibrated or user-programmed correction values.\n\nPower Management: The SAM D20 supports multiple sleep modes. Idle mode stops the CPU but keeps peripherals running; any interrupt wakes the CPU. Standby mode stops the CPU, most clocks, and Flash; only the RTC, EIC, and event system remain active; SRAM can be retained (first 8 KB); wakeup sources include external interrupts, RTC alarm, and touch detection; current consumption is approximately 3 uA in standby with RTC running. SleepWalking allows peripherals like the ADC and SERCOM to operate briefly in standby mode, triggered by events, without waking the CPU.\n\nDebug Interface: The 2-pin SWD interface (SWDIO, SWCLK) provides debug access and Flash programming. The Micro Trace Buffer (MTB) records the last 256-4096 executed instructions in a circular buffer in SRAM, providing basic instruction trace capability without requiring an external trace port.","pin_description":"
| Pin Group<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Power<\/td> | VDD, VDDIO, VDDANA, GND<\/td> | Power<\/td> | VDD: digital core supply 1.62-3.63 V; VDDIO: I\/O supply (same as VDD in this package, bonded internally); VDDANA: analog supply for ADC\/DAC\/AC (must be connected to VDD through a filtered path); GND: ground (multiple pins); VDDIO pins supply the GPIO banks; decouple each VDD\/VDDIO\/VDDANA pin with 100 nF ceramic capacitor plus a 4.7 uF bulk capacitor<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| Clock<\/td> | XIN32, XOUT32, XIN, XOUT<\/td> | Analog I\/O<\/td> | XIN32\/XOUT32: 32.768 kHz crystal for RTC; XIN\/XOUT: 0.4-32 MHz main crystal; can be left unconnected if using internal oscillators only; connect crystal with load capacitors (6-12 pF typical for 32 kHz, per crystal datasheet for main crystal)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| Reset<\/td> | RESET<\/td> | Input<\/td> | Active-low system reset with internal pull-up; asserting LOW for at least 100 ns generates a system reset; open-drain output during reset; connect 100 nF capacitor to GND for ESD filtering; also serves as SWDIO during debug (dual-function pin, selected by hardware condition at reset)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| SWD Debug<\/td> | SWDIO, SWCLK<\/td> | Digital I\/O<\/td> | Serial wire debug interface; SWDIO is shared with RESET pin; SWCLK is a dedicated pin; provides access to the Cortex-M0+ debug resources (breakpoints, watchpoints, MTB trace) and Flash programming via the NVMCTRL; connect to debug probe (Atmel ICE, J-Link, EDBG)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| GPIO Ports<\/td> | PA[00-31], PB[00-31]<\/td> | I\/O<\/td> | 52 general-purpose I\/O pins organized as Port A (32 pins) and Port B (20 pins); each pin has configurable pull-up\/pull-down, input enable, output enable, and peripheral MUX (up to 8 alternate functions); 16 pins can be mapped to external interrupts via the EIC; all pins are 3.63 V tolerant (not 5 V tolerant); pin MUX connects each GPIO to the selected peripheral function (SERCOM, TC, ADC, DAC, etc.)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| Analog<\/td> | AIN[0-19], VREF, DAC<\/td> | Analog I\/O<\/td> | 20 ADC input channels (single-ended) or 10 differential pairs; AIN0-19 shared with GPIO pins; VREF: external ADC reference input (optional, can use internal reference); DAC: 10-bit DAC output (shared with AIN0 or dedicated pin depending on configuration); AC0\/AC1: analog comparator inputs<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| Touch<\/td> | PTC X\/Y lines<\/td> | Analog<\/td> | Peripheral Touch Controller lines; shared with GPIO\/AIN pins via specific MUX configuration; up to 256 mutual capacitance channels or self-capacitance channels; PTC scanning runs autonomously with 8 uA typical current in standby mode; requires specific pin assignments per the PTC pin table in the datasheet<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| USB (not available)<\/td> | -<\/td> | -<\/td> | The SAM D20 does not include USB; use SAM D21 for USB 2.0 Full-Speed device support; otherwise pin-compatible and code-compatible<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| Thermal Pad<\/td> | EP<\/td> | Thermal<\/td> | Exposed thermal pad on bottom of TQFP-64 package; connect to PCB ground plane with multiple thermal vias; improves thermal dissipation and electrical ground connection<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|