The CD4047BM is a CMOS monostable\/astable multivibrator from TI in SOIC-14 (8.65×3.9mm). Operates in monostable (one-shot) or astable (free-running) modes with single external R and C. Timing: T=2.48RC (monostable Q output), T=4.40RC (astable period). Supply: 3V-18V. Features positive\/negative edge trigger, retrigger input, master reset, and complementary Q\/Q-bar outputs. 50% duty cycle in astable mode. Ultra-low static current: 0.02uA at 5V. 45% VDD noise immunity. Rise\/fall time: 65ns at 10V. -55\u00b0C to +125\u00b0C. RoHS compliant. Pin-compatible with HEF4047B and CD4047B variants from other manufacturers.<\/p>","protected":false},"excerpt":{"rendered":"
The CD4047BM is a CMOS monostable\/astable multivibrator from TI in SOIC-14 (8.65×3.9mm). Operates in monostable (one-shot) or astable (free-running) modes with single external R and C. Timing: T=2.48RC (monostable Q output), T=4.40RC (astable period). Supply: 3V-18V. Features positive\/negative edge trigger, retrigger input, master reset, and complementary Q\/Q-bar outputs. 50% duty cycle in astable mode. Ultra-low […]<\/p>\n","protected":false},"author":2,"featured_media":1871,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[14,13],"tags":[],"chip_brand":[138],"class_list":["post-1834","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-clock-timing-ics","category-integrated-circuits-ics","chip_brand-ti"],"acf":{"brief_explanation":"CMOS monostable\/astable multivibrator, 3V-18V, SOIC-14, retriggerable, edge-triggered","date_code":"","package_case":"SOIC-14 (8.65 x 3.9 x 1.5 mm)","in_stock":3500,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/cd4047b.pdf","price":"$0.52 (1K+ pcs)","product_introduction":"The CD4047BM is a CMOS monostable\/astable multivibrator from Texas Instruments, capable of operating in both monostable (one-shot) and astable (free-running) modes with a single external resistor and capacitor. It is a member of the CD4000B CMOS logic family and is housed in a 14-pin SOIC package.\n\nThe device provides excellent stability over the full supply voltage range of 3V to 18V and the full military temperature range of -55\u00b0C to +125\u00b0C. The timing is primarily controlled by an external resistor (R) and capacitor (C), with the pulse width in monostable mode given by T = 2.48RC (positive output) or T = 1.24RC (complement output), and the oscillation period in astable mode given by T = 4.40RC.\n\nThe CD4047BM features multiple trigger inputs for flexible operation. In monostable mode, it can be triggered by a positive-going edge on the +TRIGGER input or a negative-going edge on the -TRIGGER input. A retrigger input allows the output pulse to be extended by re-applying a trigger before the current pulse has completed. An external reset input (MR) terminates the output pulse at any time. In astable mode, the ASTABLE input enables free-running oscillation, with an optional ASTABLE input for gating.\n\nThe device provides both true (Q) and complement (Q-bar) outputs, offering complementary pulse outputs without additional logic. The output duty cycle in astable mode is approximately 50%. The rise and fall times are typically 65 ns at 10V, making the device suitable for medium-speed timing applications.\n\nThe CD4047BM is pin-compatible with the industry-standard CD4047 and can directly replace CD4047B, CD4047BC, and HEF4047B devices from other manufacturers. It is fabricated using CMOS technology, providing very low static power consumption (typically 0.02 \u00b5A at 5V, 0.1 \u00b5A at 10V, 0.5 \u00b5A at 15V) and wide noise immunity (45% of VDD typical).\n\nThe M suffix in CD4047BM denotes the SOIC-14 package for surface-mount applications. The device is also available in DIP-14 (CD4047BE) and DIP-16 (CD4047BF with additional features). Operating temperature is -55\u00b0C to +125\u00b0C (military grade). The device is RoHS compliant. TI recommends newer alternatives like the TLC555 or LM555 for simpler timing applications, or programmable timers for precision applications.","working_principle":"The CD4047BM operates as a versatile CMOS timing circuit configurable for monostable or astable operation using a single external resistor-capacitor network.\n\nInternal Architecture: The device contains a flip-flop, timing logic, trigger logic, and output buffers. The timing element is the external RC network connected between the R-C COMMON pin and the TIMING R and TIMING C pins. The internal circuit charges and discharges the external capacitor through the external resistor, with the timing period determined by the RC time constant and an internal scaling factor derived from the CMOS switching thresholds.\n\nMonostable Mode: In monostable (one-shot) mode, the device generates a single output pulse of defined width when triggered. The positive output (Q) pulse width is T = 2.48 x R x C, and the complementary output (Q-bar) pulse width is T = 1.24 x R x C. The factor of 2 difference arises because the Q output is high for the full timing cycle while Q-bar is low for the full cycle (the timing reference point differs). The device can be triggered by a positive edge on +TRIGGER or a negative edge on -TRIGGER. After triggering, the output pulse is independent of further trigger inputs unless the RETRIGGER input is used. The retrigger function allows the output pulse to be extended: if a retrigger pulse arrives before the current timing cycle completes, a new timing cycle starts from that point, extending the total output pulse duration. The external reset (MR, active high) immediately terminates the output pulse and resets the timing circuit regardless of the current state.\n\nAstable Mode: In astable (free-running) mode, the device oscillates continuously, generating a square wave output with approximately 50% duty cycle. The oscillation period is T = 4.40 x R x C, giving a frequency of f = 1\/(4.40RC). The ASTABLE input must be held high to enable oscillation. Both Q and Q-bar provide complementary square wave outputs. The astable mode can be gated by controlling the ASTABLE input, allowing the oscillation to be started and stopped under external logic control. The 50% duty cycle is inherent in the symmetric charge\/discharge cycle of the RC network through the internal CMOS switches.\n\nTiming Accuracy: The timing accuracy depends on the tolerance and stability of the external R and C components. Typical accuracy is within 1-2% at 25\u00b0C with precision components. Temperature drift is determined primarily by the external components and the internal CMOS threshold voltage temperature coefficient. For best accuracy, low-temperature-coefficient resistors (metal film) and capacitors (NPO\/COG ceramic or film) are recommended. The internal scaling factors (2.48 and 4.40) account for the ratio of CMOS switching thresholds to the supply voltage.\n\nPower Supply and Noise Immunity: The wide 3V to 18V supply range makes the device compatible with both 5V logic and higher-voltage industrial systems. The CMOS technology provides wide noise immunity (45% of VDD typical), making the timing circuit resistant to noise-induced false triggering. The very low static power consumption (sub-microampere) means the device adds negligible load to the power supply when not actively timing.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | R-C COMMON<\/td> | I\/O<\/td> | Common connection point for external timing resistor and capacitor; connect one end of R and one end of C here<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 2<\/td> | RETRIGGER<\/td> | Input<\/td> | Retrigger input for monostable mode; a positive edge restarts the timing cycle, extending the output pulse<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 3<\/td> | -TRIGGER<\/td> | Input<\/td> | Negative-edge trigger input for monostable mode; triggers on high-to-low transition<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 4<\/td> | ASTABLE<\/td> | Input<\/td> | Astable enable input; tie HIGH to enable free-running oscillation; tie LOW to inhibit oscillation<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 5<\/td> | Q<\/td> | Output<\/td> | True output; HIGH during timing pulse (monostable) or HIGH half-cycle (astable)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 6<\/td> | VSS<\/td> | Power<\/td> | Negative supply (ground); 0V reference<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 7<\/td> | MR<\/td> | Input<\/td> | Master Reset; active HIGH; resets the timing cycle and forces Q LOW; overrides all other inputs<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 8<\/td> | NC<\/td> | -<\/td> | No internal connection; leave floating or tie to GND<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 9<\/td> | NC<\/td> | -<\/td> | No internal connection; leave floating or tie to GND<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 10<\/td> | +TRIGGER<\/td> | Input<\/td> | Positive-edge trigger input for monostable mode; triggers on low-to-high transition<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 11<\/td> | Q-bar<\/td> | Output<\/td> | Complementary output; LOW during timing pulse (monostable) or LOW half-cycle (astable)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 12<\/td> | ASTABLE<\/td> | Input<\/td> | Secondary astable enable; can be used for gating the oscillator in combination with Pin 4<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 13<\/td> | TIMING C<\/td> | I\/O<\/td> | Connection point for external timing capacitor; connect capacitor between this pin and R-C COMMON<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 14<\/td> | VDD<\/td> | Power<\/td> | Positive supply voltage; 3V to 18V operating range<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
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