The SI4909DY-T1-GE3 is a Vishay Siliconix dual P-channel 40V TrenchFET power MOSFET with 8A continuous drain current and 27mohm max RDS(on) at VGS=-10V. Logic-level gate threshold. Packaged in SOIC-8, -55C to +150C junction temperature.<\/p>\n
| Configuraci\u00f3n<\/td>\n | Dual P-channel<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||
| VDS<\/td>\n | -40 V<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||
| ID<\/td>\n | -8 A per channel<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||
| RDS(on)<\/td>\n | 27 mohm max @ -10V<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||
| Qg<\/td>\n | 63 nC max<\/td>\n<\/tr>\n | ||||||||||||||||||||||||||||||||||||||||||
| PD<\/td>\n | 3.2 W<\/td>\n<\/tr>\n<\/table>\nCaracter\u00edsticas<\/h2>\nAplicaciones<\/h2>\nProduct Overview The SI4909DY-T1-GE3 is a Vishay Siliconix dual P-channel 40V TrenchFET power MOSFET with 8A continuous drain current and 27mohm max RDS(on) at VGS=-10V. Logic-level gate threshold. Packaged in SOIC-8, -55C to +150C junction temperature. Key Specifications Configuration Dual P-channel VDS -40 V ID -8 A per channel RDS(on) 27 mohm max @ -10V […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,56],"tags":[],"chip_brand":[136],"class_list":["post-8810","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-mosfets","chip_brand-vishay"],"acf":{"brief_explanation":"Dual P-ch MOSFET, 40V\/8A, 27mohm, logic-level, SOIC-8","date_code":"","package_case":"8-Pin SOIC (5.0 x 4.0 x 1.5 mm)","in_stock":887,"datasheet":"https:\/\/www.vishay.com\/docs\/70740\/si4909dy.pdf","price":"$0.52 @ 1ku","product_introduction":"The SI4909DY-T1-GE3 is a Vishay Siliconix dual P-channel TrenchFET power MOSFET in an SOIC-8 package, providing two independent P-channel MOSFETs with 40V drain-source rating and 8A continuous drain current per channel. The 27mohm maximum on-resistance at VGS=-10V ensures low conduction losses in load switch and DC-DC converter applications. The logic-level gate threshold enables direct drive from 3.3V or 5V microcontroller GPIOs. The TrenchFET trench-gate architecture achieves low RDS(on) in a compact footprint compared to planar MOSFETs. The two P-channel MOSFETs share a common source (pins 1,2,3) with independent gates and drains, making the device ideal for complementary pair or high-side switch applications. The -T1-GE3 suffix indicates tape-and-reel, halogen-free, and RoHS-compliant packaging. Each device is 100% Rg and UIS tested for reliability. Rated for -55C to +150C junction temperature.","working_principle":"The SI4909DY contains two independent P-channel enhancement-mode TrenchFET MOSFETs. Each MOSFET conducts when the gate-source voltage is more negative than the threshold voltage (typically -1.2V). When VGS = -10V (full enhancement), the channel resistance is 27mohm maximum, allowing 8A current with minimal voltage drop and power dissipation. In the off state (VGS = 0V or positive), the drain-source channel blocks voltage up to 40V with only nanoampere leakage current. The TrenchFET trench-gate structure uses vertical trenches etched into the silicon, with the gate electrode inside the trench. This geometry increases channel width per unit area, reducing RDS(on) for a given die size compared to planar structures. The body diode (inherent PN junction between body and drain) provides a reverse conduction path, useful in free-wheeling applications but may require consideration in reverse-polarity protection circuits.","pin_description":"
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