The ADS131A04IPBSR from Texas Instruments is a 4-channel, 24-bit, simultaneous-sampling delta-sigma ADC designed for precision measurement in power metering, industrial, and medical applications. It features a wide dynamic range, programmable gain amplifier, and SPI interface in a 28-pin TSSOP package.<\/p>\n
Product Overview The ADS131A04IPBSR from Texas Instruments is a 4-channel, 24-bit, simultaneous-sampling delta-sigma ADC designed for precision measurement in power metering, industrial, and medical applications. It features a wide dynamic range, programmable gain amplifier, and SPI interface in a 28-pin TSSOP package. Key Specifications Resolution: 24 bits Channels: 4 simultaneously sampling Data Rate: Up to […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[19,13],"tags":[],"chip_brand":[138],"class_list":["post-8436","post","type-post","status-publish","format-standard","hentry","category-analog-linear-ics","category-integrated-circuits-ics","chip_brand-ti"],"acf":{"brief_explanation":"4-ch 24-bit simultaneous ADC, 128kSPS, PGA, 106dB DR, TSSOP-28","date_code":"","package_case":"TSSOP-28 (4.4 \u00d7 9.7 \u00d7 1.2 mm)","in_stock":3424,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/ads131a04.pdf","price":"$5.95 @ 1ku","product_introduction":"The ADS131A04IPBSR from Texas Instruments is a 4-channel, 24-bit, simultaneous-sampling delta-sigma ADC optimized for precision measurement applications such as power metering and protective relay systems. Each channel includes a programmable gain amplifier (PGA) with gain settings from 1 to 32, enabling direct connection to a wide range of sensors and transducers. Simultaneous sampling ensures phase-aligned measurements across all four channels, critical for three-phase power metering and power quality analysis. The device achieves 106 dB dynamic range at 8 kSPS data rate with low total harmonic distortion. The integrated 2.5 V reference with low temperature drift eliminates the need for an external precision reference in most applications. An on-chip oscillator simplifies design by removing the external clock requirement, though external clock input is also supported.","working_principle":"The ADS131A04 uses a 3rd-order delta-sigma modulator per channel to convert analog input signals into high-resolution digital data. Each channel's modulator operates continuously, producing a 1-bit oversampled data stream at the modulator frequency. The integrated digital decimation filter then processes this data to produce 24-bit output words at the programmed output data rate (up to 128 kSPS). The PGA before the modulator amplifies small input signals to utilize the full modulator dynamic range. Simultaneous sampling is achieved by synchronizing all four modulators to the same clock edge, ensuring that all channels sample at exactly the same instant. The SPI interface provides read access to the conversion results and write access to configuration registers. CRC error checking on the SPI data frame ensures data integrity in noisy environments.","pin_description":"
| Pin<\/th> | Name<\/th> | Description<\/th><\/tr> | ||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | AVDD<\/td> | Analog Supply (3.0-5.5 V)<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 2<\/td> | AIN0P<\/td> | Channel 0 Positive Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 3<\/td> | AIN0N<\/td> | Channel 0 Negative Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 4<\/td> | AIN1P<\/td> | Channel 1 Positive Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 5<\/td> | AIN1N<\/td> | Channel 1 Negative Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 6<\/td> | AIN2P<\/td> | Channel 2 Positive Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 7<\/td> | AIN2N<\/td> | Channel 2 Negative Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 8<\/td> | AIN3P<\/td> | Channel 3 Positive Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 9<\/td> | AIN3N<\/td> | Channel 3 Negative Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 10<\/td> | AGND<\/td> | Analog Ground<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 11<\/td> | REFIN<\/td> | External Reference Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 12<\/td> | REFOUT<\/td> | Internal Reference Output (2.5 V)<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 13<\/td> | CLK<\/td> | External Clock Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 14<\/td> | CS<\/td> | SPI Chip Select (Active Low)<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 15<\/td> | SCLK<\/td> | SPI Clock Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 16<\/td> | DIN<\/td> | SPI Data Input<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 17<\/td> | DOUT\/DRDY<\/td> | SPI Data Output \/ Data Ready<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 18-20<\/td> | CTRL\/GPIO<\/td> | Control and GPIO Pins<\/td><\/tr> | ||||||||||||||||||||||||||||||
| 21-28<\/td> | DVDD\/DGND<\/td> | Digital Supply and Ground<\/td><\/tr><\/table>","application_scenarios":"
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