{"id":8426,"date":"2026-06-29T00:47:43","date_gmt":"2026-06-29T00:47:43","guid":{"rendered":"https:\/\/materialparts.com\/5m160ze64i5n\/"},"modified":"2026-06-29T00:47:43","modified_gmt":"2026-06-29T00:47:43","slug":"5m160ze64i5n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/5m160ze64i5n\/","title":{"rendered":"5M160ZE64I5N"},"content":{"rendered":"<h2>Productos<\/h2>\n<p>The 5M160ZE64I5N is a MAX V CPLD from Intel (formerly Altera), featuring 160 logic elements (128 macrocells) in a low-cost, low-power, non-volatile architecture. It offers instant-on configuration (0.5 ms or less), standby current as low as 25 \u00b5A, and MultiVolt I\/O supporting 1.2 V to 3.3 V logic levels, packaged in a 64-pin EQFP.<\/p>\n<h2>Especificaciones<\/h2>\n<ul>\n<li>Logic Elements: 160 (128 equivalent macrocells)<\/li>\n<li>Pin-to-Pin Delay: 7.5 ns<\/li>\n<li>User Flash Memory: 8 Kbits (up to 1000 read\/write cycles)<\/li>\n<li>Core Supply: 1.8 V single external supply<\/li>\n<li>MultiVolt I\/O: 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V<\/li>\n<li>Standby Current: 25 \u00b5A typ<\/li>\n<li>Internal Oscillator: Yes<\/li>\n<li>JTAG ISP: IEEE 1149.1 compliant<\/li>\n<li>I\/O Banks: 2<\/li>\n<li>Maximum I\/O: 54<\/li>\n<li>Operating Temperature: -40\u00b0C to +100\u00b0C (I grade)<\/li>\n<li>Package: EQFP-64 (7 \u00d7 7 mm)<\/li>\n<\/ul>\n<h2>Caracter\u00edsticas<\/h2>\n<ul>\n<li>Non-volatile, instant-on CPLD (no external configuration needed)<\/li>\n<li>Ultra-low standby power (25 \u00b5A)<\/li>\n<li>Emulated LVDS output up to 304 Mbps<\/li>\n<li>Emulated RSDS output up to 200 Mbps<\/li>\n<li>Programmable slew rate and drive strength per pin<\/li>\n<li>Schmitt trigger inputs for noise tolerance<\/li>\n<li>Hot-socket compliant<\/li>\n<li>On-chip user flash memory for non-volatile storage<\/li>\n<\/ul>\n<h2>Aplicaciones<\/h2>\n<ul>\n<li>Board-level glue logic and address decoding<\/li>\n<li>I\/O expansion and bus bridging<\/li>\n<li>Power sequencing and supervisory logic<\/li>\n<li>Configuration controller for FPGAs<\/li>\n<li>Industrial control state machines<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p>Product Overview The 5M160ZE64I5N is a MAX V CPLD from Intel (formerly Altera), featuring 160 logic elements (128 macrocells) in a low-cost, low-power, non-volatile architecture. It offers instant-on configuration (0.5 ms or less), standby current as low as 25 \u00b5A, and MultiVolt I\/O supporting 1.2 V to 3.3 V logic levels, packaged in a 64-pin [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,25],"tags":[],"chip_brand":[196],"class_list":["post-8426","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-microcontrollers-mcu","chip_brand-intel"],"acf":{"brief_explanation":"MAX V CPLD, 160 LE \/ 128 MC, 7.5ns, 1.8V core, EQFP-64","date_code":"","package_case":"EQFP-64 (7 \u00d7 7 \u00d7 1.55 mm)","in_stock":14149,"datasheet":"https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/hb\/max-v\/mv5v1.pdf","price":"$6.77 @ 1ku","product_introduction":"The 5M160ZE64I5N is a member of Intel's MAX V CPLD family, built on a low-cost, low-power, non-volatile architecture using 180 nm process technology. With 160 logic elements organized as 128 equivalent macrocells and 8 Kbits of user flash memory, the device provides flexible combinational and sequential logic capabilities. The instant-on configuration (0.5 ms) eliminates the need for external configuration devices, simplifying board design. The MultiVolt I\/O interface supports 1.2 V to 3.3 V logic levels across two I\/O banks, enabling mixed-voltage system integration. Standby current as low as 25 \u00b5A makes it ideal for battery-powered applications. The device supports JTAG in-system programming and features Schmitt trigger inputs for noise-tolerant operation.","working_principle":"The MAX V CPLD uses a non-volatile flash-based architecture where the configuration is stored on-chip, enabling instant-on operation without external configuration devices. Logic is implemented through Logic Array Blocks (LABs), each containing 10 logic elements (LEs). Each LE contains a 4-input look-up table (LUT), a programmable register, and carry\/chain logic. Interconnect routing between LABs is configured during programming. The MultiVolt I\/O architecture separates core (1.8 V) and I\/O (1.2-3.3 V) supplies, allowing direct connection to different voltage domains. The 8 Kbit user flash memory block provides non-volatile storage for calibration data or serial numbers. JTAG interface enables in-system programming and boundary-scan testing per IEEE 1149.1.","pin_description":"<table border=\"1\"><tr><th>Pin<\/th><th>Name<\/th><th>Description<\/th><\/tr><tr><td>1<\/td><td>VCCIO1<\/td><td>I\/O Bank 1 Supply (1.2-3.3V)<\/td><\/tr><tr><td>2<\/td><td>IO\/DATA0<\/td><td>Dual-purpose I\/O \/ JTAG Data<\/td><\/tr><tr><td>3-6<\/td><td>IO<\/td><td>General Purpose I\/O<\/td><\/tr><tr><td>7<\/td><td>GND<\/td><td>Ground<\/td><\/tr><tr><td>8-15<\/td><td>IO<\/td><td>General Purpose I\/O<\/td><\/tr><tr><td>16<\/td><td>TCK<\/td><td>JTAG Clock<\/td><\/tr><tr><td>17<\/td><td>TMS<\/td><td>JTAG Mode Select<\/td><\/tr><tr><td>18<\/td><td>TDI<\/td><td>JTAG Data Input<\/td><\/tr><tr><td>19<\/td><td>TDO<\/td><td>JTAG Data Output<\/td><\/tr><tr><td>20-31<\/td><td>IO<\/td><td>General Purpose I\/O<\/td><\/tr><tr><td>32<\/td><td>VCCINT<\/td><td>Core Supply (1.8V)<\/td><\/tr><tr><td>33-48<\/td><td>IO\/GND<\/td><td>I\/O and Ground<\/td><\/tr><tr><td>49<\/td><td>VCCIO2<\/td><td>I\/O Bank 2 Supply (1.2-3.3V)<\/td><\/tr><tr><td>50-64<\/td><td>IO\/GND<\/td><td>I\/O and Ground<\/td><\/tr><\/table>","application_scenarios":"<ul><li><b>Board-Level Glue Logic<\/b>: Address decoding, chip select generation, and bus arbitration in multi-device systems<\/li><li><b>Power Sequencing<\/b>: Multi-rail power-up\/down control with precision timing for FPGAs and processors<\/li><li><b>I\/O Expansion<\/b>: Interface bridging between different voltage domains (1.2V-3.3V) using MultiVolt I\/O<\/li><li><b>FPGA Configuration Controller<\/b>: Non-volatile storage and sequencing for SRAM-based FPGA boot-up<\/li><li><b>Industrial State Machines<\/b>: Deterministic, instant-on control logic for safety-critical industrial applications<\/li><\/ul>","alternative_models":"<table border=\"1\"><tr><th>Model<\/th><th>Brand<\/th><th>LEs<\/th><th>MCs<\/th><th>Package<\/th><\/tr><tr><td>5M40ZE64I5N<\/td><td>Intel<\/td><td>40<\/td><td>32<\/td><td>EQFP-64<\/td><\/tr><tr><td>5M80ZE64I5N<\/td><td>Intel<\/td><td>80<\/td><td>64<\/td><td>EQFP-64<\/td><\/tr><tr><td>EPM240F100I5N<\/td><td>Intel<\/td><td>240<\/td><td>192<\/td><td>TQFP-100<\/td><\/tr><tr><td>XC2C64A-7VQG44I<\/td><td>Xilinx<\/td><td>64<\/td><td>64<\/td><td>QFP-44<\/td><\/tr><tr><td>MachXO2-1200HC<\/td><td>Lattice<\/td><td>1280<\/td><td>-<\/td><td>TQFP-100<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8426","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=8426"}],"version-history":[{"count":0,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8426\/revisions"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=8426"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=8426"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=8426"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=8426"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}