The AD7705BRZ is a 16-bit Sigma-Delta ADC from Analog Devices with built-in programmable gain amplifier (PGA), gain 1-128, 2 differential input channels, SPI interface, in a DIP-16 package, suitable for low-frequency measurement and sensor interfaces.<\/p>\n
AD7705BRZ Overview The AD7705BRZ is a 16-bit Sigma-Delta ADC from Analog Devices with built-in programmable gain amplifier (PGA), gain 1-128, 2 differential input channels, SPI interface, in a DIP-16 package, suitable for low-frequency measurement and sensor interfaces. Key Features Resolution: 16-bit 2 differential input channels Programmable gain: 1-128 SPI interface Supply voltage: 2.7V-5.25V Output data […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[19,13],"tags":[],"chip_brand":[165],"class_list":["post-8036","post","type-post","status-publish","format-standard","hentry","category-analog-linear-ics","category-integrated-circuits-ics","chip_brand-adi"],"acf":{"brief_explanation":"16-bit Sigma-Delta ADC, 2-ch, low power, SOIC-16","date_code":"","package_case":"SOIC-16 (10.30 x 7.50 x 2.65 mm)","in_stock":3243,"datasheet":"https:\/\/www.analog.com\/media\/en\/technical-documentation\/data-sheets\/ad7705_7706.pdf","price":"$7.80 @ 1ku","product_introduction":"The AD7705BRZ is a 2-channel, 16-bit sigma-delta analog-to-digital converter from Analog Devices in a 16-lead wide SOIC package. It integrates a programmable gain amplifier (PGA) with gains from 1 to 128, allowing direct connection of low-level transducer signals without external signal conditioning. The device operates from a single 2.7 V to 3.3 V or 4.75 V to 5.25 V supply, dissipating only 1 mW maximum at 3 V with 8 uA standby current. A 3-wire SPI-compatible serial interface provides simple microcontroller connectivity. Self-calibration and system calibration options eliminate gain and offset errors, making it ideal for low-frequency measurement applications such as pressure, temperature, and weight sensing.","working_principle":"The AD7705BRZ employs a second-order sigma-delta modulator followed by a digital decimation filter to achieve 16-bit resolution with no missing codes. The analog input is first buffered by an optional input buffer (configurable via register) and then applied to the programmable gain amplifier, which amplifies signals from 1x to 128x. The PGA output feeds the sigma-delta modulator, which oversamples the input at a high rate and produces a 1-bit data stream. The digital filter processes this stream to produce a 16-bit output word at the programmed update rate (50 Hz to 500 Hz for a 2.4576 MHz master clock). The first notch frequency of the sinc-3 digital filter can be programmed via the filter register, simultaneously setting the output update rate and the -3 dB frequency. The device performs continuous self-calibration in the background, compensating for offset and gain drift. System calibration modes allow the user to apply zero-scale and full-scale reference points, enabling the AD7705 to calibrate the entire signal path including external components. The input multiplexer selects between two fully differential input channels, and the polarity (unipolar or bipolar) is programmable per channel.","pin_description":"
| Pin<\/th> | Name<\/th> | Description<\/th><\/tr> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | SCLK<\/td> | Serial clock input; Schmitt-triggered, SPI-compatible<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 2<\/td> | MCLK IN<\/td> | Master clock input; connect crystal or external clock (400 kHz to 2.5 MHz)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 3<\/td> | MCLK OUT<\/td> | Master clock output; connect crystal between pins 2 and 3<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 4<\/td> | CS<\/td> | Chip select; active low, enables the serial interface<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 5<\/td> | RESET<\/td> | Reset input; active low, resets all control logic and registers<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 6<\/td> | AIN2(+)<\/td> | Channel 2 positive analog input<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 7<\/td> | AIN1(+)<\/td> | Channel 1 positive analog input<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 8<\/td> | AIN1(-)<\/td> | Channel 1 negative analog input<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 9<\/td> | REFIN(-)<\/td> | Reference negative input; typically connected to GND or AVSS<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 10<\/td> | REFIN(+)<\/td> | Reference positive input; sets the full-scale range<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 11<\/td> | AIN2(-)<\/td> | Channel 2 negative analog input<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 12<\/td> | DIN<\/td> | Serial data input; register write data from MCU<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 13<\/td> | DOUT<\/td> | Serial data output; conversion results read by MCU<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 14<\/td> | DRDY<\/td> | Data ready output; active low, indicates new conversion data available<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 15<\/td> | VDD<\/td> | Power supply (2.7 V to 3.3 V or 4.75 V to 5.25 V)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 16<\/td> | GND<\/td> | Ground reference<\/td><\/tr><\/table>","application_scenarios":"
|