{"id":8015,"date":"2026-06-28T06:44:56","date_gmt":"2026-06-28T06:44:56","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls173n\/"},"modified":"2026-06-28T11:43:51","modified_gmt":"2026-06-28T11:43:51","slug":"sn74ls173n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls173n\/","title":{"rendered":"SN74LS173N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS173N from Texas Instruments is a 4-bit D-type register with 3-state outputs and dual input\/output enable controls \u2014 the TTL equivalent of the CD4076 for bus-oriented register applications in a 16-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n
Funci\u00f3n<\/td>\n4-bit D-type register with 3-state outputs<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
Register Bits<\/td>\n4<\/td>\n<\/tr>\n
Reloj<\/td>\nPositive edge triggered<\/td>\n<\/tr>\n
Data Enable<\/td>\nG1\u0304, G2\u0304 (both LOW = data enabled; any HIGH = register holds)<\/td>\n<\/tr>\n
Output Enable<\/td>\nOE1\u0304, OE2\u0304 (both LOW = outputs active; any HIGH = high-Z)<\/td>\n<\/tr>\n
Clear<\/td>\nAsynchronous, active-HIGH (CLR)<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n20-30ns typical<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • 4-bit edge-triggered D register<\/li>\n
  • 3-state outputs for bus connection<\/li>\n
  • Dual data enable (G1\u0304, G2\u0304) \u2014 hold when disabled<\/li>\n
  • Dual output enable (OE1\u0304, OE2\u0304) \u2014 high-Z when disabled<\/li>\n
  • Asynchronous clear<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Bus registers in microprocessor systems<\/li>\n
    • I\/O port registers<\/li>\n
    • Multi-master bus isolation<\/li>\n
    • Data buffering<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS173N from Texas Instruments is a 4-bit D-type register with 3-state outputs and dual input\/output enable controls \u2014 the TTL equivalent of the CD4076 for bus-oriented register applications in a 16-pin PDIP package. Key Specifications Function 4-bit D-type register with 3-state outputs Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-8015","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"4-bit D register, 3-state, dual data\/output enable, async clear, LS TTL, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":3000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls173a.pdf","price":"$0.75 @ 1ku","product_introduction":"The SN74LS173N from Texas Instruments is a 4-bit positive-edge-triggered D register with 3-state outputs and separate input\/output enable controls. It captures 4 bits of data on the rising clock edge and holds them until the next qualified clock. The data enable inputs (G1\u0304, G2\u0304, both active-LOW) control whether new data is loaded: when both are LOW, D0-D3 are loaded on the next rising CLK edge; when either is HIGH, the register holds its current value (ignoring D inputs and clock). This is different from the CD4076 which forces inputs to zero when disabled \u2014 the 74173 holds its value instead, which is usually more useful. The output enable inputs (OE1\u0304, OE2\u0304, both active-LOW) control the 3-state outputs: when both are LOW, Q0-Q3 drive the bus; when either is HIGH, Q0-Q3 go to high-impedance. The asynchronous clear (CLR=HIGH) resets all bits to 0. The 74173 is the standard TTL bus register for microprocessor systems where multiple registers share a common data bus. The N suffix denotes the PDIP-16 package.","working_principle":"The SN74LS173N captures data on the rising edge of CLK, subject to the data enable inputs. When both G1\u0304 and G2\u0304 are LOW (data enabled): on the rising CLK edge, D0-D3 are stored in the flip-flops and appear on Q0-Q3 (if outputs are enabled). When either G1\u0304 or G2\u0304 is HIGH (data disabled): the register holds its current value on the next clock edge; D inputs are ignored. This 'hold' behavior is achieved by feeding the current Q output back to the D input when the enable is inactive. Output control: when both OE1\u0304 and OE2\u0304 are LOW, Q0-Q3 drive the bus (active). When either OE1\u0304 or OE2\u0304 is HIGH, Q0-Q3 go to high-impedance (disconnected). For multi-register bus systems: a 2-to-4 decoder drives the OE inputs of four 74173 registers; only one register's outputs are enabled at a time; the selected register drives the shared bus. Clear: CLR=HIGH asynchronously resets all bits to 0, overriding clock and data inputs. Data enable can be used as a clock enable: tie G1\u0304 to an enable signal; G2\u0304 to LOW; the register only loads new data when the enable is active.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>OE1\u0304<\/td>Input<\/td>Output enable 1 (active-LOW; HIGH = high-Z)<\/td><\/tr>\n
      2<\/td>Q0<\/td>Output<\/td>Register output bit 0 (3-state)<\/td><\/tr>\n
      3<\/td>Q1<\/td>Output<\/td>Register output bit 1 (3-state)<\/td><\/tr>\n
      4<\/td>Q2<\/td>Output<\/td>Register output bit 2 (3-state)<\/td><\/tr>\n
      5<\/td>Q3<\/td>Output<\/td>Register output bit 3 (3-state)<\/td><\/tr>\n
      6<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      7<\/td>OE2\u0304<\/td>Input<\/td>Output enable 2 (active-LOW; HIGH = high-Z)<\/td><\/tr>\n
      8<\/td>G2\u0304<\/td>Input<\/td>Data enable 2 (active-LOW; HIGH = hold)<\/td><\/tr>\n
      9<\/td>G1\u0304<\/td>Input<\/td>Data enable 1 (active-LOW; HIGH = hold)<\/td><\/tr>\n
      10<\/td>D3<\/td>Input<\/td>Register data input bit 3<\/td><\/tr>\n
      11<\/td>D2<\/td>Input<\/td>Register data input bit 2<\/td><\/tr>\n
      12<\/td>D1<\/td>Input<\/td>Register data input bit 1<\/td><\/tr>\n
      13<\/td>D0<\/td>Input<\/td>Register data input bit 0<\/td><\/tr>\n
      14<\/td>CLR<\/td>Input<\/td>Asynchronous clear (active-HIGH)<\/td><\/tr>\n
      15<\/td>CLK<\/td>Input<\/td>Clock (positive edge)<\/td><\/tr>\n
      16<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Multi-Register Bus:<\/strong> Four 74173s share output bus; 2-to-4 decoder drives OE inputs; each register captures data from same input bus at different times; selected register drives output bus<\/li>\n
      • Clock-Enabled Register:<\/strong> G1\u0304 = clock enable; G2\u0304 = LOW; register loads data only when enable active; holds when enable inactive<\/li>\n
      • Output Port:<\/strong> MCU data bus \u2192 D0-D3; MCU write strobe \u2192 CLK; MCU address decode \u2192 OE1\u0304; register holds output data; drives peripheral bus<\/li>\n
      • Input Port:<\/strong> Peripheral data \u2192 D0-D3; MCU read strobe \u2192 CLK (via address decode); OE enables bus drive; register buffers input to MCU bus<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS173N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS173D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC173D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC173N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT173D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT173N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n<\/table>\n

        The 74173 is a 4-Bit D-Type Register with 3-State Output. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8015","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=8015"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8015\/revisions"}],"predecessor-version":[{"id":8124,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8015\/revisions\/8124"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=8015"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=8015"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=8015"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=8015"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}