{"id":8014,"date":"2026-06-28T06:44:55","date_gmt":"2026-06-28T06:44:55","guid":{"rendered":"https:\/\/materialparts.com\/cd4076be\/"},"modified":"2026-06-28T11:43:53","modified_gmt":"2026-06-28T11:43:53","slug":"cd4076be","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/cd4076be\/","title":{"rendered":"CD4076BE"},"content":{"rendered":"

Productos<\/h2>\n

The CD4076BE from Texas Instruments is a 4-bit D-type register with 3-state outputs and input\/output disable controls \u2014 a registered bus transceiver for multi-master bus systems in a 16-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n
Funci\u00f3n<\/td>\n4-bit D-type register with 3-state outputs<\/td>\n<\/tr>\n
Technology<\/td>\nCD4000B CMOS<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n3V to 18V<\/td>\n<\/tr>\n
Register Bits<\/td>\n4<\/td>\n<\/tr>\n
Reloj<\/td>\nPositive edge triggered<\/td>\n<\/tr>\n
Data Disable<\/td>\nDI1, DI2 (both LOW = data enabled; any HIGH = input forced LOW)<\/td>\n<\/tr>\n
Output Disable<\/td>\nDO1, DO2 (both LOW = outputs enabled; any HIGH = high-Z)<\/td>\n<\/tr>\n
Clear<\/td>\nAsynchronous, active-HIGH (RST)<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n200ns typical @ VDD=10V<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n-55\u00b0C to +125\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-16 (19.3 x 9.4mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • 4-bit edge-triggered D register<\/li>\n
  • 3-state outputs for bus connection<\/li>\n
  • Independent input and output disable controls<\/li>\n
  • Asynchronous clear<\/li>\n
  • 3V-18V wide supply range<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Bus registers<\/li>\n
    • I\/O port latches<\/li>\n
    • Data buffering with bus isolation<\/li>\n
    • Multi-master bus systems<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The CD4076BE from Texas Instruments is a 4-bit D-type register with 3-state outputs and input\/output disable controls \u2014 a registered bus transceiver for multi-master bus systems in a 16-pin PDIP package. Key Specifications Function 4-bit D-type register with 3-state outputs Technology CD4000B CMOS Supply Voltage 3V to 18V Register Bits 4 Clock Positive […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-8014","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"4-bit D register, 3-state outputs, input\/output disable, CMOS 3-18V, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 9.4 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":2000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/cd4076b.pdf","price":"$0.50 @ 1ku","product_introduction":"The CD4076BE from Texas Instruments is a 4-bit edge-triggered D register with 3-state outputs and separate input\/output disable controls. It captures 4 bits of data on the rising clock edge and holds them until the next clock. The 3-state outputs allow multiple CD4076 registers to share a common bus \u2014 only one register drives the bus at a time. The input disable (DI1, DI2) controls what gets loaded: when both DI1 and DI2 are LOW, the D inputs pass through normally; when either DI1 or DI2 is HIGH, the inputs are forced LOW internally (zeros are loaded on the next clock). This allows one input to serve as a data enable while the other provides a zero-load function. The output disable (DO1, DO2) controls the 3-state outputs: when both are LOW, outputs drive the bus; when either is HIGH, outputs go to high-impedance. The two disable inputs each provide independent gating, allowing flexible control logic. The asynchronous clear (RST=HIGH) resets all flip-flops to 0. The BE suffix denotes the PDIP-16 package.","working_principle":"The CD4076BE captures data on the rising edge of CLK. On each rising CLK edge, the D0-D3 inputs (after input disable gating) are stored in the four D flip-flops. The stored data appears on Q0-Q3 when the output enables are active (both DO1 and DO2 LOW). Input disable: DI1 and DI2 are ANDed (both must be LOW for data to pass). If either DI1 or DI2 is HIGH, the internal data path is forced to 0 \u2014 zeros are loaded on the next clock instead of the D inputs. This is useful for selectively loading data or clearing the register via clock. Output disable: DO1 and DO2 are ANDed (both must be LOW for outputs to drive). If either DO1 or DO2 is HIGH, Q0-Q3 go to high-impedance (disconnected from the bus). Multiple CD4076 registers can share a bus; only one has its outputs enabled at a time (controlled by a decoder driving DO1 or DO2). Clear: RST=HIGH asynchronously resets all flip-flops to 0, regardless of CLK, D inputs, or disable controls.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>DO1<\/td>Input<\/td>Output disable 1 (HIGH = outputs high-Z)<\/td><\/tr>\n
      2<\/td>Q0<\/td>Output<\/td>Register output bit 0 (3-state)<\/td><\/tr>\n
      3<\/td>Q1<\/td>Output<\/td>Register output bit 1 (3-state)<\/td><\/tr>\n
      4<\/td>DO2<\/td>Input<\/td>Output disable 2 (HIGH = outputs high-Z)<\/td><\/tr>\n
      5<\/td>D0<\/td>Input<\/td>Register data input bit 0<\/td><\/tr>\n
      6<\/td>D1<\/td>Input<\/td>Register data input bit 1<\/td><\/tr>\n
      7<\/td>RST<\/td>Input<\/td>Asynchronous reset (active HIGH)<\/td><\/tr>\n
      8<\/td>VSS<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>CLK<\/td>Input<\/td>Clock (positive edge triggered)<\/td><\/tr>\n
      10<\/td>DI1<\/td>Input<\/td>Data input disable 1 (HIGH = force input LOW)<\/td><\/tr>\n
      11<\/td>DI2<\/td>Input<\/td>Data input disable 2 (HIGH = force input LOW)<\/td><\/tr>\n
      12<\/td>D2<\/td>Input<\/td>Register data input bit 2<\/td><\/tr>\n
      13<\/td>D3<\/td>Input<\/td>Register data input bit 3<\/td><\/tr>\n
      14<\/td>Q2<\/td>Output<\/td>Register output bit 2 (3-state)<\/td><\/tr>\n
      15<\/td>Q3<\/td>Output<\/td>Register output bit 3 (3-state)<\/td><\/tr>\n
      16<\/td>VDD<\/td>Power<\/td>Supply (3V to 18V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Bus Register:<\/strong> 4-bit bus data \u2192 D0-D3; CLK captures data; DO1\/DO2 from address decoder; only selected register drives bus<\/li>\n
      • I\/O Port:<\/strong> MCU writes data \u2192 D0-D3 with CLK; MCU reads \u2192 Q0-Q3 with DO enable; DI1 used as write enable; bidirectional I\/O port<\/li>\n
      • Multi-Port Register:<\/strong> Two CD4076s share output bus; one reads port A, other reads port B; address decoder selects which drives bus via DO<\/li>\n
      • Zero-Load:<\/strong> DI1 = load enable (LOW=load data, HIGH=load zeros); DI2 = tied LOW; selectively load data or clear register via clock<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        CD4076BM<\/td>TI<\/td>SOIC-16 surface-mount version with identical logic function and 3-18V range<\/td>SOIC-16<\/td>3-18V<\/td><\/tr>\n
        CD4076BE<\/td>TI<\/td>Through-hole DIP version for prototyping and legacy board repair<\/td>DIP-16<\/td>3-18V<\/td><\/tr>\n
        HEF4076BT<\/td>NXP<\/td>Pin-compatible CMOS version with improved ESD protection and 3-15V supply<\/td>SOIC-16<\/td>3-15V<\/td><\/tr>\n
        MC144076BDR2G<\/td>onsemi<\/td>Pin-compatible equivalent with RoHS compliance and AEC-Q100 automotive option<\/td>SOIC-16<\/td>3-18V<\/td><\/tr>\n
        74LS173D<\/td>TI\/Nexperia<\/td>HC CMOS version with higher speed and 2-6V supply for modern logic systems<\/td>SOIC-16<\/td>2-6V<\/td><\/tr>\n
        74LS173N<\/td>TI\/Nexperia<\/td>HC CMOS through-hole version for prototyping with 2-6V supply range<\/td>DIP-16<\/td>2-6V<\/td><\/tr>\n
        74LS173D<\/td>Nexperia<\/td>HCT version with TTL-compatible inputs for mixed 5V TTL\/CMOS systems<\/td>SOIC-16<\/td>4.5-5.5V<\/td><\/tr>\n<\/table>\n

        CD4076 is the CMOS 4000-series 4-bit register with 3-state operating over the wide 3-18V supply range. The HEF4076 (NXP) and MC144076 (onsemi) are direct pin-compatible equivalents. For higher speed at the cost of narrower voltage range, the 74LS173 HC\/HCT families offer significantly faster propagation delay and lower power consumption at 2-6V. Surface-mount versions use the BM\/M suffix (SOIC); through-hole versions use the BE suffix (DIP).<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8014","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=8014"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8014\/revisions"}],"predecessor-version":[{"id":8125,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8014\/revisions\/8125"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=8014"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=8014"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=8014"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=8014"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}