{"id":8004,"date":"2026-06-28T06:38:17","date_gmt":"2026-06-28T06:38:17","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls20n-2\/"},"modified":"2026-06-28T11:44:08","modified_gmt":"2026-06-28T11:44:08","slug":"sn74ls20n-2","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls20n-2\/","title":{"rendered":"SN74LS20N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS20N from Texas Instruments contains two independent 4-input NAND gates in a 14-pin PDIP package \u2014 essential for decoding and multi-condition gating where all four conditions must be met.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n
Number of Gates<\/td>\n2 (dual 4-input NAND)<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n10-15ns typical<\/td>\n<\/tr>\n
Output Drive<\/td>\nIOL = 8mA, IOH = -0.4mA<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Dual 4-input NAND gates<\/li>\n
  • Output LOW only when ALL four inputs are HIGH<\/li>\n
  • Active-LOW output enables multi-condition decoding<\/li>\n
  • 10-15ns propagation delay<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Address decoding (4 conditions \u2192 1 chip select)<\/li>\n
    • Multi-condition gating<\/li>\n
    • Control logic<\/li>\n
    • General TTL logic<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS20N from Texas Instruments contains two independent 4-input NAND gates in a 14-pin PDIP package \u2014 essential for decoding and multi-condition gating where all four conditions must be met. Key Specifications Number of Gates 2 (dual 4-input NAND) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V Propagation Delay 10-15ns typical […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-8004","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual 4-input NAND gate, LS TTL, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":5000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls20a.pdf","price":"$0.35 @ 1ku","product_introduction":"The SN74LS20N from Texas Instruments contains two independent 4-input NAND gates. Each gate implements Y = NOT(A AND B AND C AND D); the output goes LOW only when all four inputs are HIGH. This is the 4-input extension of the 2-input NAND (7400) and is critical for address decoding and multi-condition logic. In address decoding, the 4-input NAND can decode a specific 4-bit address pattern: connect the 4 address lines (or their complements) so that the NAND output goes LOW only for the target address. For example, to decode address 1011: connect A3 (direct), A2 (inverted), A1 (direct), A0 (direct) to the NAND inputs; the output goes LOW only when A3=1, A2=0, A1=1, A0=1. The 4-input NAND provides 16 possible input combinations; only one produces a LOW output. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each 4-input NAND gate in the SN74LS20N performs Y = (A\u00b7B\u00b7C\u00b7D)'. The output is LOW only when all four inputs A, B, C, and D are simultaneously HIGH. For any other combination (at least one input LOW), the output is HIGH. The 4-input NAND is essentially an AND function followed by inversion, but implemented as a single gate for lower delay. By DeMorgan's theorem: Y = A' + B' + C' + D' (OR of complements). This means the NAND output is HIGH if ANY input is LOW \u2014 making it useful as an 'any-inactive' detector. For address decoding: connect address lines (direct or inverted) so that the target address presents all HIGH inputs; the NAND output goes LOW, selecting the target device. For multi-condition gating: all four conditions must be active (HIGH) for the output to go LOW (active); any inactive condition forces the output HIGH. Unused inputs on a 4-input NAND should be tied HIGH (VCC) to not affect the logic; tying them LOW would force the output permanently HIGH.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1A<\/td>Input<\/td>Gate 1 input A<\/td><\/tr>\n
      2<\/td>1B<\/td>Input<\/td>Gate 1 input B<\/td><\/tr>\n
      3<\/td>NC<\/td>\u2014<\/td>No connection<\/td><\/tr>\n
      4<\/td>1C<\/td>Input<\/td>Gate 1 input C<\/td><\/tr>\n
      5<\/td>1D<\/td>Input<\/td>Gate 1 input D<\/td><\/tr>\n
      6<\/td>1Y<\/td>Output<\/td>Gate 1 output<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>2Y<\/td>Output<\/td>Gate 2 output<\/td><\/tr>\n
      9<\/td>2A<\/td>Input<\/td>Gate 2 input A<\/td><\/tr>\n
      10<\/td>2B<\/td>Input<\/td>Gate 2 input B<\/td><\/tr>\n
      11<\/td>NC<\/td>\u2014<\/td>No connection<\/td><\/tr>\n
      12<\/td>2C<\/td>Input<\/td>Gate 2 input C<\/td><\/tr>\n
      13<\/td>2D<\/td>Input<\/td>Gate 2 input D<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>\n

      SN74LS20N uses the PDIP-14 package with standard 74LS TTL pinout: VCC at Pin 14, GND at Pin 7. Each NAND gate has four inputs and one open-collector output \u2014 Gate 1: Pins 1-4 (inputs), Pin 6 (output); Gate 2: Pins 9-12 (inputs), Pin 8 (output). Pins 5 and 13 are not connected. The LS technology provides typical propagation delay of 15ns. The open-collector outputs allow wired-AND connections and level shifting to higher voltages. For push-pull active pull-up outputs, use SN74HC20N or SN74HCT20N which maintain the same pinout. The 5400 military-grade variant offers -55\u00b0C to +125\u00b0C operation.<\/p>","application_scenarios":"

        \n
      • 4-Bit Address Decode:<\/strong> 4 address lines (with inverters as needed) \u2192 A,B,C,D; Y goes LOW only for target address; Y \u2192 chip select (active-LOW)<\/li>\n
      • Multi-Condition Enable:<\/strong> 4 enable conditions \u2192 A,B,C,D; Y = LOW only when ALL enables are active; any condition missing = Y HIGH<\/li>\n
      • 2-to-4 Line Decoder:<\/strong> 2 address lines and their complements \u2192 two NAND gates; Y1 decodes address 00, Y2 decodes address 11; partial decoding<\/li>\n
      • Combined with 7410:<\/strong> 7420 (4-input) + 7410 (3-input) NAND gates create complex decode logic for multi-bit addresses<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS20N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS20D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC20D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC20N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT20D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT20N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC20D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC20N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC20D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC20N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7420 is a Dual 4-Input NAND Gate. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8004","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=8004"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8004\/revisions"}],"predecessor-version":[{"id":8135,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8004\/revisions\/8135"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=8004"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=8004"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=8004"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=8004"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}