{"id":8002,"date":"2026-06-28T06:38:14","date_gmt":"2026-06-28T06:38:14","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls125n\/"},"modified":"2026-06-28T11:44:11","modified_gmt":"2026-06-28T11:44:11","slug":"sn74ls125n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls125n\/","title":{"rendered":"SN74LS125N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS125N from Texas Instruments contains four independent bus buffer gates with 3-state outputs controlled by active-LOW enables \u2014 essential for sharing a common data bus among multiple sources in a 14-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n
Funci\u00f3n<\/td>\nQuad bus buffer with 3-state outputs<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
Buffers<\/td>\n4 (independent, non-inverting)<\/td>\n<\/tr>\n
Output Enable<\/td>\nActive-LOW (OE\u0304, per buffer)<\/td>\n<\/tr>\n
Output Type<\/td>\n3-state (HIGH, LOW, or high-impedance)<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n8-13ns typical<\/td>\n<\/tr>\n
Output Drive<\/td>\nIOL = 24mA, IOH = -2.6mA<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Four non-inverting buffers with 3-state outputs<\/li>\n
  • Active-LOW output enable per buffer<\/li>\n
  • High-impedance output when disabled<\/li>\n
  • 24mA sink current for bus driving<\/li>\n
  • Diode-clamped inputs<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Bus buffer \/ driver<\/li>\n
    • I\/O port isolation<\/li>\n
    • Multi-source data bus sharing<\/li>\n
    • Level translation (5V to 3.3V with pull-ups)<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS125N from Texas Instruments contains four independent bus buffer gates with 3-state outputs controlled by active-LOW enables \u2014 essential for sharing a common data bus among multiple sources in a 14-pin PDIP package. Key Specifications Function Quad bus buffer with 3-state outputs Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-8002","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Quad non-inverting bus buffer, 3-state, active-LOW enable, LS TTL, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":5000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls125a.pdf","price":"$0.40 @ 1ku","product_introduction":"The SN74LS125N from Texas Instruments contains four independent non-inverting buffer gates with 3-state (tri-state) outputs. Each buffer has a data input (A), a data output (Y), and an active-LOW output enable (OE\u0304). When OE\u0304 is LOW, Y = A (the buffer drives the bus). When OE\u0304 is HIGH, Y enters a high-impedance state (electrically disconnected from the bus). The 3-state output is the key feature: multiple 74125 buffers (or other 3-state devices) can share a common bus, and only one drives the bus at a time while all others are in high-Z. The 24mA sink current provides strong bus driving capability. The non-inverting function means the output is the same polarity as the input. The 74125 is the complement of the 74126 (which has active-HIGH enables). For bus applications: multiple data sources connect through 74125 buffers to a common bus; a decoder selects which buffer is enabled (only one at a time); the selected source drives the bus. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each buffer in the SN74LS125N operates as a non-inverting pass gate with 3-state control. When OE\u0304 (output enable) is LOW: Y = A; the buffer actively drives the bus line HIGH or LOW. When OE\u0304 is HIGH: Y enters high-impedance (high-Z) state; the output is effectively disconnected from the bus; the bus line is free to be driven by another device. The 3-state output behaves like a switch: enabled = switch closed (Y follows A); disabled = switch open (Y floats). Only one 3-state device should drive a given bus line at any time; if two devices drive conflicting logic levels, bus contention occurs (excessive current flow, potential damage). A decoder or logic ensures exactly one enable is active at a time. The high-Z state is NOT the same as a HIGH logic level \u2014 it's a floating state. Pull-up or pull-down resistors are often used on 3-state buses to define a known logic level when no device is driving. The 24mA sink capability allows the 74125 to drive heavily loaded bus lines.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1OE\u0304<\/td>Input<\/td>Buffer 1 output enable (active LOW)<\/td><\/tr>\n
      2<\/td>1A<\/td>Input<\/td>Buffer 1 data input<\/td><\/tr>\n
      3<\/td>1Y<\/td>Output<\/td>Buffer 1 output (3-state)<\/td><\/tr>\n
      4<\/td>2OE\u0304<\/td>Input<\/td>Buffer 2 output enable (active LOW)<\/td><\/tr>\n
      5<\/td>2A<\/td>Input<\/td>Buffer 2 data input<\/td><\/tr>\n
      6<\/td>2Y<\/td>Output<\/td>Buffer 2 output (3-state)<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>3Y<\/td>Output<\/td>Buffer 3 output (3-state)<\/td><\/tr>\n
      9<\/td>3A<\/td>Input<\/td>Buffer 3 data input<\/td><\/tr>\n
      10<\/td>3OE\u0304<\/td>Input<\/td>Buffer 3 output enable (active LOW)<\/td><\/tr>\n
      11<\/td>4Y<\/td>Output<\/td>Buffer 4 output (3-state)<\/td><\/tr>\n
      12<\/td>4A<\/td>Input<\/td>Buffer 4 data input<\/td><\/tr>\n
      13<\/td>4OE\u0304<\/td>Input<\/td>Buffer 4 output enable (active LOW)<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • 4-Source Bus:<\/strong> 4 data sources \u2192 1A-4A; decoder drives 1OE\u0304-4OE\u0304 (one LOW at a time); all Y outputs on shared bus; selected source drives bus<\/li>\n
      • Bi-Directional Bus:<\/strong> 74125 for output direction + 74125 for input direction; direction signal selects which buffer group is active<\/li>\n
      • I\/O Isolation:<\/strong> MCU I\/O pin \u2192 A; OE\u0304 from direction control; Y \u2192 peripheral bus; disconnect MCU from bus when not communicating<\/li>\n
      • Level Translation:<\/strong> 3.3V signal \u2192 A (with current-limit resistor); 5V bus on Y; OE\u0304 = LOW; 74125 safely passes 3.3V as valid TTL HIGH<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS125N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS125D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC125D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC125N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT125D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT125N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74LVC125D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC125N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 74125 is a Quad Bus Buffer with 3-State Output (Active-Low Enable). Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8002","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=8002"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8002\/revisions"}],"predecessor-version":[{"id":8137,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/8002\/revisions\/8137"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=8002"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=8002"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=8002"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=8002"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}