{"id":7997,"date":"2026-06-28T06:38:09","date_gmt":"2026-06-28T06:38:09","guid":{"rendered":"https:\/\/materialparts.com\/cd4042be\/"},"modified":"2026-06-28T11:44:20","modified_gmt":"2026-06-28T11:44:20","slug":"cd4042be","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/cd4042be\/","title":{"rendered":"CD4042BE"},"content":{"rendered":"

Productos<\/h2>\n

The CD4042BE from Texas Instruments is a quad clocked D-type latch with clock polarity control and complementary outputs \u2014 four transparent latches in a single 16-pin PDIP package that can be configured for either level-triggered mode.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n
Funci\u00f3n<\/td>\nQuad clocked D latch (4 transparent latches)<\/td>\n<\/tr>\n
Technology<\/td>\nCD4000B CMOS<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n3V to 18V<\/td>\n<\/tr>\n
Number of Latches<\/td>\n4 (independent D inputs, common CLK)<\/td>\n<\/tr>\n
Clock Polarity<\/td>\nProgrammable via POLARITY input<\/td>\n<\/tr>\n
Outputs<\/td>\nQ and Q\u0304 per latch (complementary, buffered)<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n500ns typical @ VDD=5V; 150ns @ 10V<\/td>\n<\/tr>\n
Max Clock Frequency<\/td>\n8MHz @ VDD=10V<\/td>\n<\/tr>\n
Corriente de salida<\/td>\n2.4mA sink \/ 2.4mA source @ VDD=10V<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n-55\u00b0C to +125\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-16 (19.3 x 9.4mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Four D-type latches with common clock<\/li>\n
  • Clock polarity control (active-HIGH or active-LOW clock)<\/li>\n
  • Complementary Q and Q\u0304 outputs from each latch<\/li>\n
  • Transparent mode: outputs follow D while clock is active<\/li>\n
  • Latched mode: outputs hold when clock transitions<\/li>\n
  • 3V-18V wide supply range<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Buffer storage \/ data holding registers<\/li>\n
    • Address latches for multiplexed buses<\/li>\n
    • Debouncing circuits<\/li>\n
    • General digital storage<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The CD4042BE from Texas Instruments is a quad clocked D-type latch with clock polarity control and complementary outputs \u2014 four transparent latches in a single 16-pin PDIP package that can be configured for either level-triggered mode. Key Specifications Function Quad clocked D latch (4 transparent latches) Technology CD4000B CMOS Supply Voltage 3V to […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7997","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Quad clocked D latch, polarity control, complementary outputs, CMOS 3-18V, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 9.4 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":4000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/cd4042b.pdf","price":"$0.243 @ 1ku","product_introduction":"The CD4042BE from Texas Instruments contains four D-type transparent latches with a common clock and a unique polarity control input. The POLARITY pin determines whether the latches are transparent when CLOCK is LOW (POLARITY=0) or when CLOCK is HIGH (POLARITY=1). When the clock is at the 'active' level (as defined by POLARITY), the Q outputs follow their respective D inputs (transparent mode). When the clock transitions away from the active level, the data present at the D inputs at that moment is latched and held at the Q outputs until the next active clock phase. Each latch provides both Q and Q\u0304 (complementary) outputs, all fully buffered with balanced CMOS push-pull drivers. The common clock simplifies system design when all four latches must capture data simultaneously (e.g., address latching for multiplexed address\/data buses). The polarity feature eliminates the need for an external inverter: if the system clock is active-HIGH, set POLARITY=1; if active-LOW, set POLARITY=0. The 3V-18V supply range covers all common digital voltage levels. The BE suffix denotes the PDIP-16 package.","working_principle":"Each of the four latches in the CD4042BE operates as a transparent D latch with the following behavior controlled by the CLOCK and POLARITY inputs. When POLARITY=0: the latches are transparent when CLOCK=LOW (Q follows D while CLOCK is LOW). When CLOCK transitions from LOW to HIGH (rising edge), the D input value is captured and held. When POLARITY=1: the latches are transparent when CLOCK=HIGH (Q follows D while CLOCK is HIGH). When CLOCK transitions from HIGH to LOW (falling edge), the D input value is captured and held. In both cases, the opposite clock transition re-enables transparency. This is summarized as: the data is transferred to the outputs during the clock level equal to the POLARITY value, and latched on the opposite clock edge. The Q\u0304 output always provides the complement of Q. The four latches share the same CLOCK and POLARITY inputs, so they all operate in the same mode simultaneously. For address latching in a multiplexed bus system: the address appears on the bus during the active clock phase; the CD4042 captures it on the inactive transition; the latched address is stable while data occupies the bus.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>Q4<\/td>Output<\/td>Latch 4 complementary output (Q\u03044)<\/td><\/tr>\n
      2<\/td>Q1<\/td>Output<\/td>Latch 1 true output (Q1)<\/td><\/tr>\n
      3<\/td>Q\u03041<\/td>Output<\/td>Latch 1 complementary output (Q\u03041)<\/td><\/tr>\n
      4<\/td>D1<\/td>Input<\/td>Latch 1 data input<\/td><\/tr>\n
      5<\/td>CLOCK<\/td>Input<\/td>Common clock (all 4 latches)<\/td><\/tr>\n
      6<\/td>POLARITY<\/td>Input<\/td>Clock polarity (0=transparent on LOW, 1=transparent on HIGH)<\/td><\/tr>\n
      7<\/td>D2<\/td>Input<\/td>Latch 2 data input<\/td><\/tr>\n
      8<\/td>VSS<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>Q\u03042<\/td>Output<\/td>Latch 2 complementary output (Q\u03042)<\/td><\/tr>\n
      10<\/td>Q2<\/td>Output<\/td>Latch 2 true output (Q2)<\/td><\/tr>\n
      11<\/td>Q\u03043<\/td>Output<\/td>Latch 3 complementary output (Q\u03043)<\/td><\/tr>\n
      12<\/td>Q3<\/td>Output<\/td>Latch 3 true output (Q3)<\/td><\/tr>\n
      13<\/td>D3<\/td>Input<\/td>Latch 3 data input<\/td><\/tr>\n
      14<\/td>D4<\/td>Input<\/td>Latch 4 data input<\/td><\/tr>\n
      15<\/td>Q\u03044<\/td>Output<\/td>Latch 4 complementary output (Q\u03044)<\/td><\/tr>\n
      16<\/td>VDD<\/td>Power<\/td>Supply (3V to 18V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Address Latch:<\/strong> Multiplexed address\/data bus \u2192 D1-D4; ALE signal \u2192 CLOCK; POLARITY=1 (transparent when HIGH); address captured on falling ALE edge; stable address for external memory<\/li>\n
      • Data Hold Register:<\/strong> Sensor data \u2192 D1-D4; sample pulse \u2192 CLOCK; POLARITY=0; data captured on rising clock edge; held between samples<\/li>\n
      • Debouncer:<\/strong> Switch \u2192 D1; oscillator \u2192 CLOCK; POLARITY=1; switch state sampled at clock rate; output free of bounce<\/li>\n
      • 4-Bit Comparator Storage:<\/strong> CD4063 comparator outputs \u2192 D1-D4; clock latches comparison result; Q outputs held for next processing stage<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        CD4042BM<\/td>TI<\/td>SOIC-16 surface-mount version with identical logic function and 3-18V range<\/td>SOIC-16<\/td>3-18V<\/td><\/tr>\n
        CD4042BE<\/td>TI<\/td>Through-hole DIP version for prototyping and legacy board repair<\/td>DIP-16<\/td>3-18V<\/td><\/tr>\n
        HEF4042BT<\/td>NXP<\/td>Pin-compatible CMOS version with improved ESD protection and 3-15V supply<\/td>SOIC-16<\/td>3-15V<\/td><\/tr>\n
        MC144042BDR2G<\/td>onsemi<\/td>Pin-compatible equivalent with RoHS compliance and AEC-Q100 automotive option<\/td>SOIC-16<\/td>3-18V<\/td><\/tr>\n
        74LS75D<\/td>TI\/Nexperia<\/td>HC CMOS version with higher speed and 2-6V supply for modern logic systems<\/td>SOIC-16<\/td>2-6V<\/td><\/tr>\n
        74LS75N<\/td>TI\/Nexperia<\/td>HC CMOS through-hole version for prototyping with 2-6V supply range<\/td>DIP-16<\/td>2-6V<\/td><\/tr>\n
        74LS75D<\/td>Nexperia<\/td>HCT version with TTL-compatible inputs for mixed 5V TTL\/CMOS systems<\/td>SOIC-16<\/td>4.5-5.5V<\/td><\/tr>\n<\/table>\n

        CD4042 is the CMOS 4000-series quad clocked d latch operating over the wide 3-18V supply range. The HEF4042 (NXP) and MC144042 (onsemi) are direct pin-compatible equivalents. For higher speed at the cost of narrower voltage range, the 74LS75 HC\/HCT families offer significantly faster propagation delay and lower power consumption at 2-6V. Surface-mount versions use the BM\/M suffix (SOIC); through-hole versions use the BE suffix (DIP).<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7997","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7997"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7997\/revisions"}],"predecessor-version":[{"id":8141,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7997\/revisions\/8141"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7997"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7997"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7997"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7997"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}