{"id":7994,"date":"2026-06-28T06:32:26","date_gmt":"2026-06-28T06:32:26","guid":{"rendered":"https:\/\/materialparts.com\/cd4027be\/"},"modified":"2026-06-28T11:44:24","modified_gmt":"2026-06-28T11:44:24","slug":"cd4027be","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/cd4027be\/","title":{"rendered":"CD4027BE"},"content":{"rendered":"

Productos<\/h2>\n

The CD4027BE from Texas Instruments contains two independent J-K flip-flops with set and reset, positive-edge triggered \u2014 the CMOS counterpart of the 7476 for 3V-18V systems in a 16-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n
Number of Flip-Flops<\/td>\n2 (dual, independent)<\/td>\n<\/tr>\n
Technology<\/td>\nCD4000B CMOS<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n3V to 18V<\/td>\n<\/tr>\n
Trigger Type<\/td>\nPositive-edge (rising edge of CLK)<\/td>\n<\/tr>\n
Set (S)<\/td>\nActive-HIGH (asynchronous, sets Q=1)<\/td>\n<\/tr>\n
Reset (R)<\/td>\nActive-HIGH (asynchronous, sets Q=0)<\/td>\n<\/tr>\n
Max Clock Frequency<\/td>\n10MHz typical @ VDD=10V<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n150ns typical @ VDD=10V<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n-55\u00b0C to +125\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-16 (19.3 x 9.4mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Dual J-K positive-edge-triggered flip-flops<\/li>\n
  • Active-HIGH set and reset (unlike TTL’s active-LOW)<\/li>\n
  • Toggle mode: J=K=VDD<\/li>\n
  • 3V-18V wide supply range<\/li>\n
  • Complementary outputs (Q and NOT-Q)<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Toggle flip-flop \/ frequency divider<\/li>\n
    • Counter building blocks<\/li>\n
    • Control sequencing<\/li>\n
    • Data storage<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The CD4027BE from Texas Instruments contains two independent J-K flip-flops with set and reset, positive-edge triggered \u2014 the CMOS counterpart of the 7476 for 3V-18V systems in a 16-pin PDIP package. Key Specifications Number of Flip-Flops 2 (dual, independent) Technology CD4000B CMOS Supply Voltage 3V to 18V Trigger Type Positive-edge (rising edge of […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7994","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual J-K flip-flop, positive-edge, set\/reset active-HIGH, CMOS 3-18V, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 9.4 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":4000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/cd4027b.pdf","price":"$0.50 @ 1ku","product_introduction":"The CD4027BE from Texas Instruments contains two independent J-K positive-edge-triggered flip-flops with active-HIGH asynchronous set (S) and reset (R). It is the CMOS counterpart of the TTL 7476, but with two key differences: (1) it triggers on the positive (rising) clock edge (like the 7474 D flip-flop), and (2) the set and reset inputs are active-HIGH (unlike the 7476's active-LOW PRE and CLR). The J-K functionality provides four operating modes: hold (J=0,K=0), set (J=1,K=0), reset (J=0,K=1), and toggle (J=1,K=1). The toggle mode is the most common use: connecting J and K to VDD causes Q to toggle on each rising clock edge, dividing the clock by 2. The wide 3V-18V supply range makes the CD4027 suitable for battery-powered and multi-voltage systems where TTL can't operate. The active-HIGH set and reset are consistent with CMOS logic conventions. Two CD4027 flip-flops can be cascaded in toggle mode to divide by 4, or used independently for dual control functions. The BE suffix denotes the PDIP-16 package.","working_principle":"Each J-K flip-flop in the CD4027BE operates on the rising edge of CLK. The J and K inputs determine what happens on the next rising clock edge: J=0,K=0 \u2192 Q holds; J=1,K=0 \u2192 Q=1 (set); J=0,K=1 \u2192 Q=0 (reset); J=1,K=1 \u2192 Q toggles. The asynchronous set (S=HIGH) forces Q=1 regardless of CLK, J, K; the asynchronous reset (R=HIGH) forces Q=0. Both S and R are active-HIGH. For normal operation, S and R must both be LOW. If both S and R are HIGH simultaneously, both Q and NOT-Q go HIGH (invalid state). For toggle mode: J=K=VDD (both HIGH); each rising clock edge toggles Q; Q frequency = CLK\/2. For frequency division by 4: cascade \u2014 Q1 \u2192 CLK2; Q2 = CLK\/4. For a D flip-flop equivalent: connect J=data and K=NOT-data (through an inverter). The CD4027's positive-edge triggering is compatible with CD4013 (D flip-flop) and CD4017 (counter), making it easy to build synchronous systems with a common clock.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1Q<\/td>Output<\/td>Flip-flop 1 Q output<\/td><\/tr>\n
      2<\/td>1NOT-Q<\/td>Output<\/td>Flip-flop 1 complementary output<\/td><\/tr>\n
      3<\/td>1CLK<\/td>Input<\/td>Flip-flop 1 clock (positive edge)<\/td><\/tr>\n
      4<\/td>1R<\/td>Input<\/td>Flip-flop 1 reset (active HIGH)<\/td><\/tr>\n
      5<\/td>1K<\/td>Input<\/td>Flip-flop 1 K input<\/td><\/tr>\n
      6<\/td>1J<\/td>Input<\/td>Flip-flop 1 J input<\/td><\/tr>\n
      7<\/td>1S<\/td>Input<\/td>Flip-flop 1 set (active HIGH)<\/td><\/tr>\n
      8<\/td>VSS<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>2S<\/td>Input<\/td>Flip-flop 2 set (active HIGH)<\/td><\/tr>\n
      10<\/td>2J<\/td>Input<\/td>Flip-flop 2 J input<\/td><\/tr>\n
      11<\/td>2K<\/td>Input<\/td>Flip-flop 2 K input<\/td><\/tr>\n
      12<\/td>2R<\/td>Input<\/td>Flip-flop 2 reset (active HIGH)<\/td><\/tr>\n
      13<\/td>2CLK<\/td>Input<\/td>Flip-flop 2 clock (positive edge)<\/td><\/tr>\n
      14<\/td>2NOT-Q<\/td>Output<\/td>Flip-flop 2 complementary output<\/td><\/tr>\n
      15<\/td>2Q<\/td>Output<\/td>Flip-flop 2 Q output<\/td><\/tr>\n
      16<\/td>VDD<\/td>Power<\/td>Supply (3V to 18V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Toggle \/ \u00f72:<\/strong> J=K=VDD; clock on CLK; Q toggles each rising edge; Q = CLK\/2<\/li>\n
      • 2-Bit Counter:<\/strong> FF1: J=K=VDD, CLK=input; Q1\u2192CLK2; FF2: J=K=VDD; Q2,Q1 count 00\u219201\u219210\u219211\u219200<\/li>\n
      • Controlled Toggle:<\/strong> J=K=enable; enable=HIGH \u2192 toggle on clock; enable=LOW \u2192 hold; gated oscillator<\/li>\n
      • D Flip-Flop:<\/strong> J=data, K=NOT-data (via inverter); Q follows data on rising CLK edge<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        CD4027BM<\/td>TI<\/td>SOIC-16 surface-mount version with identical logic function and 3-18V range<\/td>SOIC-16<\/td>3-18V<\/td><\/tr>\n
        CD4027BE<\/td>TI<\/td>Through-hole DIP version for prototyping and legacy board repair<\/td>DIP-16<\/td>3-18V<\/td><\/tr>\n
        HEF4027BT<\/td>NXP<\/td>Pin-compatible CMOS version with improved ESD protection and 3-15V supply<\/td>SOIC-16<\/td>3-15V<\/td><\/tr>\n
        MC144027BDR2G<\/td>onsemi<\/td>Pin-compatible equivalent with RoHS compliance and AEC-Q100 automotive option<\/td>SOIC-16<\/td>3-18V<\/td><\/tr>\n
        74HC109D<\/td>TI\/Nexperia<\/td>HC CMOS version with higher speed and 2-6V supply for modern logic systems<\/td>SOIC-16<\/td>2-6V<\/td><\/tr>\n
        74HC109N<\/td>TI\/Nexperia<\/td>HC CMOS through-hole version for prototyping with 2-6V supply range<\/td>DIP-16<\/td>2-6V<\/td><\/tr>\n
        74HCT109D<\/td>Nexperia<\/td>HCT version with TTL-compatible inputs for mixed 5V TTL\/CMOS systems<\/td>SOIC-16<\/td>4.5-5.5V<\/td><\/tr>\n<\/table>\n

        CD4027 is the CMOS 4000-series dual j-k flip-flop operating over the wide 3-18V supply range. The HEF4027 (NXP) and MC144027 (onsemi) are direct pin-compatible equivalents. For higher speed at the cost of narrower voltage range, the 74HC109 HC\/HCT families offer significantly faster propagation delay and lower power consumption at 2-6V. Surface-mount versions use the BM\/M suffix (SOIC); through-hole versions use the BE suffix (DIP).<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7994","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7994"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7994\/revisions"}],"predecessor-version":[{"id":8144,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7994\/revisions\/8144"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7994"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7994"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7994"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7994"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}