{"id":7985,"date":"2026-06-28T06:25:45","date_gmt":"2026-06-28T06:25:45","guid":{"rendered":"https:\/\/materialparts.com\/cd4518be\/"},"modified":"2026-06-28T11:44:40","modified_gmt":"2026-06-28T11:44:40","slug":"cd4518be","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/cd4518be\/","title":{"rendered":"CD4518BE"},"content":{"rendered":"

Productos<\/h2>\n

The CD4518BE from Texas Instruments contains two independent synchronous BCD up-counters with clock and enable inputs, each capable of counting 0-9 in BCD in a 16-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n
Funci\u00f3n<\/td>\nDual BCD synchronous up-counter<\/td>\n<\/tr>\n
Technology<\/td>\nCD4000B CMOS<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n3V to 18V<\/td>\n<\/tr>\n
Counter Type<\/td>\nBCD decade (0-9)<\/td>\n<\/tr>\n
Count Direction<\/td>\nUp only<\/td>\n<\/tr>\n
Trigger<\/td>\nPositive-edge on CLK (when EN=HIGH) or negative-edge on EN (when CLK=LOW)<\/td>\n<\/tr>\n
Restablecer<\/td>\nAsynchronous, active HIGH (MR)<\/td>\n<\/tr>\n
Max Clock Frequency<\/td>\n6MHz typical @ VDD=10V<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n-55\u00b0C to +125\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Dual BCD up-counters in one package<\/li>\n
  • Two clocking options: CLK edge or EN edge<\/li>\n
  • Asynchronous master reset (active HIGH)<\/li>\n
  • Cascadable via Q3 output<\/li>\n
  • 3V-18V CMOS operation<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Frequency counting<\/li>\n
    • Event counting (0-9 per digit)<\/li>\n
    • Multi-digit BCD displays<\/li>\n
    • Timing and sequencing<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The CD4518BE from Texas Instruments contains two independent synchronous BCD up-counters with clock and enable inputs, each capable of counting 0-9 in BCD in a 16-pin PDIP package. Key Specifications Function Dual BCD synchronous up-counter Technology CD4000B CMOS Supply Voltage 3V to 18V Counter Type BCD decade (0-9) Count Direction Up only Trigger […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7985","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual BCD up-counter, CMOS 3-18V, dual clock\/enable, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":4000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/cd4518b.pdf","price":"$0.50 @ 1ku","product_introduction":"The CD4518BE from Texas Instruments contains two independent BCD (Binary-Coded Decimal) up-counters. Each counter counts from 0 to 9 in BCD (0000 to 1001) and rolls over to 0. The dual clocking scheme offers flexibility: (1) Clock on the CLK pin with EN=HIGH \u2014 counting on the rising edge of CLK. (2) Clock on the EN pin with CLK=LOW \u2014 counting on the falling edge of EN. This allows either positive-edge or negative-edge triggering. The asynchronous master reset (MR=HIGH) immediately resets all four outputs to 0 regardless of clock. For multi-digit counting, the Q3 output (MSB) of one counter connects to the CLK of the next counter: when the first counter rolls from 9 to 0, Q3 transitions from HIGH to LOW and back \u2014 a positive edge on the next counter's CLK, incrementing the next digit. The CD4518 is simpler than the CD4029 (no up\/down or binary\/decade selection) but provides two counters in one 16-pin package, making it efficient for multi-digit BCD displays. The BE suffix denotes the PDIP-16 package.","working_principle":"Each BCD counter in the CD4518BE is a 4-bit synchronous counter that sequences through 0000, 0001, 0010, ... 1001, then rolls over to 0000. The counter advances when: (a) a rising edge occurs on CLK while EN is HIGH, or (b) a falling edge occurs on EN while CLK is LOW. When neither condition is met, the counter holds its value. The MR (master reset) input is asynchronous: when MR=HIGH, all Q outputs go to 0 immediately regardless of CLK and EN states. For normal counting, MR must be LOW. The Q3 output goes HIGH at count 8 and returns LOW at count 0 (rollover), providing a carry signal for cascading. To cascade for 2-digit (0-99) counting: Q3 of counter 1 \u2192 CLK of counter 2; EN of both counters tied HIGH; MR of both tied together for simultaneous reset. For frequency division: Q1 divides clock by 2, Q2 by 4, Q3 provides a pulse every 10 clocks (decade divider). The BCD outputs (Q1-Q4) connect directly to BCD-to-7-segment decoders like CD4511 for display driving.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1CLK<\/td>Input<\/td>Counter 1 clock (positive edge when 1EN=HIGH)<\/td><\/tr>\n
      2<\/td>1EN<\/td>Input<\/td>Counter 1 clock enable (HIGH=enable, negative edge triggers when 1CLK=LOW)<\/td><\/tr>\n
      3<\/td>1Q1<\/td>Output<\/td>Counter 1 output LSB<\/td><\/tr>\n
      4<\/td>1Q2<\/td>Output<\/td>Counter 1 output bit 2<\/td><\/tr>\n
      5<\/td>1Q3<\/td>Output<\/td>Counter 1 output bit 3<\/td><\/tr>\n
      6<\/td>1Q4<\/td>Output<\/td>Counter 1 output MSB<\/td><\/tr>\n
      7<\/td>1MR<\/td>Input<\/td>Counter 1 master reset (active HIGH)<\/td><\/tr>\n
      8<\/td>VSS<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>2MR<\/td>Input<\/td>Counter 2 master reset (active HIGH)<\/td><\/tr>\n
      10<\/td>2Q4<\/td>Output<\/td>Counter 2 output MSB<\/td><\/tr>\n
      11<\/td>2Q3<\/td>Output<\/td>Counter 2 output bit 3<\/td><\/tr>\n
      12<\/td>2Q2<\/td>Output<\/td>Counter 2 output bit 2<\/td><\/tr>\n
      13<\/td>2Q1<\/td>Output<\/td>Counter 2 output LSB<\/td><\/tr>\n
      14<\/td>2EN<\/td>Input<\/td>Counter 2 clock enable<\/td><\/tr>\n
      15<\/td>2CLK<\/td>Input<\/td>Counter 2 clock<\/td><\/tr>\n
      16<\/td>VDD<\/td>Power<\/td>Supply (3V to 18V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • 2-Digit Counter (0-99):<\/strong> Pulses \u2192 1CLK (1EN=HIGH); 1Q4 \u2192 2CLK (2EN=HIGH); both MR tied together; Q1-Q4 each \u2192 CD4511 \u2192 7-segment display<\/li>\n
      • Decade Divider:<\/strong> Clock \u2192 1CLK; 1Q4 output = pulse every 10 clocks; divide-by-10 frequency divider<\/li>\n
      • Divide-by-100:<\/strong> Two CD4518 counters cascaded; 1Q4 \u2192 2CLK; 2Q4 \u2192 3CLK (second chip); 100 pulses per output pulse<\/li>\n
      • Event Counter:<\/strong> Sensor pulses \u2192 1CLK; 1EN=HIGH; 1MR=reset button; Q1-Q4 read by MCU or displayed<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        CD4518BM<\/td>TI<\/td>SOIC-16 surface-mount version with identical logic function and 3-18V range<\/td>SOIC-16<\/td>3-18V<\/td><\/tr>\n
        CD4518BE<\/td>TI<\/td>Through-hole DIP version for prototyping and legacy board repair<\/td>DIP-16<\/td>3-18V<\/td><\/tr>\n
        HEF4518BT<\/td>NXP<\/td>Pin-compatible CMOS version with improved ESD protection and 3-15V supply<\/td>SOIC-16<\/td>3-15V<\/td><\/tr>\n
        MC144518BDR2G<\/td>onsemi<\/td>Pin-compatible equivalent with RoHS compliance and AEC-Q100 automotive option<\/td>SOIC-16<\/td>3-18V<\/td><\/tr>\n
        74HC4518D<\/td>TI\/Nexperia<\/td>HC CMOS version with higher speed and 2-6V supply for modern logic systems<\/td>SOIC-16<\/td>2-6V<\/td><\/tr>\n
        74HC4518N<\/td>TI\/Nexperia<\/td>HC CMOS through-hole version for prototyping with 2-6V supply range<\/td>DIP-16<\/td>2-6V<\/td><\/tr>\n
        74HCT4518D<\/td>Nexperia<\/td>HCT version with TTL-compatible inputs for mixed 5V TTL\/CMOS systems<\/td>SOIC-16<\/td>4.5-5.5V<\/td><\/tr>\n<\/table>\n

        CD4518 is the CMOS 4000-series dual bcd up counter operating over the wide 3-18V supply range. The HEF4518 (NXP) and MC144518 (onsemi) are direct pin-compatible equivalents. For higher speed at the cost of narrower voltage range, the 74HC4518 HC\/HCT families offer significantly faster propagation delay and lower power consumption at 2-6V. Surface-mount versions use the BM\/M suffix (SOIC); through-hole versions use the BE suffix (DIP).<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7985","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7985"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7985\/revisions"}],"predecessor-version":[{"id":8152,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7985\/revisions\/8152"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7985"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7985"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7985"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7985"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}