{"id":7980,"date":"2026-06-28T06:25:38","date_gmt":"2026-06-28T06:25:38","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls139n\/"},"modified":"2026-06-28T11:44:47","modified_gmt":"2026-06-28T11:44:47","slug":"sn74ls139n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls139n\/","title":{"rendered":"SN74LS139N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS139N from Texas Instruments contains two independent 2-line to 4-line decoder\/demultiplexers with active-LOW outputs and enable, ideal for address decoding and data demultiplexing in a 16-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n
Funci\u00f3n<\/td>\nDual 2-line to 4-line decoder\/demultiplexer<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
Select Inputs<\/td>\nA, B per decoder<\/td>\n<\/tr>\n
Enable<\/td>\nG (active-LOW, per decoder)<\/td>\n<\/tr>\n
Outputs<\/td>\nY0-Y3 (active-LOW, per decoder)<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n13\u201325ns typical<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Two independent 2-to-4 decoders in one package<\/li>\n
  • Active-LOW enables and outputs<\/li>\n
  • Can be used as demultiplexer (G = data input)<\/li>\n
  • Cascadable for wider decoding<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Memory address decoding<\/li>\n
    • I\/O port decoding<\/li>\n
    • Data demultiplexing<\/li>\n
    • Chip select generation<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS139N from Texas Instruments contains two independent 2-line to 4-line decoder\/demultiplexers with active-LOW outputs and enable, ideal for address decoding and data demultiplexing in a 16-pin PDIP package. Key Specifications Function Dual 2-line to 4-line decoder\/demultiplexer Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V Select Inputs A, B per decoder […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7980","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual 2-to-4 decoder\/demux, active-LOW, LS TTL, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":5000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls139.pdf","price":"$0.35 @ 1ku","product_introduction":"The SN74LS139N from Texas Instruments contains two independent 2-line to 4-line decoders\/demultiplexers. Each decoder has two select inputs (A, B) that determine which of the four active-LOW outputs (Y0-Y3) is driven LOW. The active-LOW enable (G) must be LOW for any output to be active; when G is HIGH, all outputs are HIGH regardless of select inputs. The 74139 is the workhorse of address decoding: with two address lines, it can generate four mutually exclusive active-LOW chip-select signals. Two 74139 decoders can be cascaded to create a 3-to-8 decoder (equivalent to 74138) using the enable of one decoder as the third select line. As a demultiplexer, the G input becomes the data input: the data on G is routed to the selected output (inverted), while unselected outputs remain HIGH. The N suffix denotes the PDIP-16 through-hole package.","working_principle":"Each decoder in the SN74LS139N implements the logic: when G=LOW, exactly one of Y0-Y3 is LOW based on the select inputs. When BA=00, Y0=LOW (all others HIGH); BA=01, Y1=LOW; BA=10, Y2=LOW; BA=11, Y3=LOW. When G=HIGH, all outputs are HIGH regardless of BA. The function: Yi = (G + (B'\u00b7A' for i=0) + (B'\u00b7A for i=1) + (B\u00b7A' for i=2) + (B\u00b7A for i=3))'. For a 3-to-8 decoder: connect A2 to 1G (decoder 1 enable) and through an inverter to 2G (decoder 2 enable); A0 and A1 connect to both decoders' A and B inputs. When A2=LOW, decoder 1 is active (outputs 0-3); when A2=HIGH, decoder 2 is active (outputs 4-7). As a demultiplexer: serial data on G; A,B select the output; the selected output follows G (inverted), while unselected outputs stay HIGH. When G goes LOW, the selected output goes LOW; when G goes HIGH, all outputs go HIGH.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1G<\/td>Input<\/td>Decoder 1 enable (active LOW)<\/td><\/tr>\n
      2<\/td>1A<\/td>Input<\/td>Decoder 1 select A (LSB)<\/td><\/tr>\n
      3<\/td>1B<\/td>Input<\/td>Decoder 1 select B (MSB)<\/td><\/tr>\n
      4<\/td>1Y0<\/td>Output<\/td>Decoder 1 output 0 (active LOW)<\/td><\/tr>\n
      5<\/td>1Y1<\/td>Output<\/td>Decoder 1 output 1 (active LOW)<\/td><\/tr>\n
      6<\/td>1Y2<\/td>Output<\/td>Decoder 1 output 2 (active LOW)<\/td><\/tr>\n
      7<\/td>1Y3<\/td>Output<\/td>Decoder 1 output 3 (active LOW)<\/td><\/tr>\n
      8<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>2Y3<\/td>Output<\/td>Decoder 2 output 3 (active LOW)<\/td><\/tr>\n
      10<\/td>2Y2<\/td>Output<\/td>Decoder 2 output 2 (active LOW)<\/td><\/tr>\n
      11<\/td>2Y1<\/td>Output<\/td>Decoder 2 output 1 (active LOW)<\/td><\/tr>\n
      12<\/td>2Y0<\/td>Output<\/td>Decoder 2 output 0 (active LOW)<\/td><\/tr>\n
      13<\/td>2B<\/td>Input<\/td>Decoder 2 select B (MSB)<\/td><\/tr>\n
      14<\/td>2A<\/td>Input<\/td>Decoder 2 select A (LSB)<\/td><\/tr>\n
      15<\/td>2G<\/td>Input<\/td>Decoder 2 enable (active LOW)<\/td><\/tr>\n
      16<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Chip Select Generation:<\/strong> 2 address lines \u2192 A,B; G tied LOW; Y0-Y3 \u2192 chip selects for 4 peripheral ICs; one address decodes to one active-LOW CS<\/li>\n
      • 3-to-8 Decoder:<\/strong> A2 \u2192 1G (direct) and 2G (via inverter); A0,A1 \u2192 both decoders; 8 active-LOW outputs for memory chip selects<\/li>\n
      • Demultiplexer:<\/strong> Serial data on G; A,B select output; data appears (inverted) on selected output; 1-to-4 data routing<\/li>\n
      • I\/O Port Decode:<\/strong> High address bits \u2192 74139; Y0=IO port 0, Y1=IO port 1, etc.; combined with RD\/WR for read\/write strobes<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS139N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS139D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC139D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC139N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT139D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT139N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74LVC139D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-16<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC139N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-16<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 74139 is a Dual 2-Line to 4-Line Decoder\/Demultiplexer. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7980","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7980"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7980\/revisions"}],"predecessor-version":[{"id":8156,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7980\/revisions\/8156"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7980"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7980"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7980"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7980"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}