{"id":7969,"date":"2026-06-28T06:17:38","date_gmt":"2026-06-28T06:17:38","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls20n\/"},"modified":"2026-06-28T11:45:03","modified_gmt":"2026-06-28T11:45:03","slug":"sn74ls20n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls20n\/","title":{"rendered":"SN74LS20N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS20N from Texas Instruments contains two independent 4-input positive NAND gates in a 14-pin PDIP package \u2014 essential for implementing wide AND\/NAND logic functions with minimal chip count.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n
Number of Gates<\/td>\n2 (dual 4-input NAND)<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n15ns typical @ 5V<\/td>\n<\/tr>\n
Output Drive (IOL\/IOH)<\/td>\n8mA \/ -0.4mA<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Dual 4-input NAND gates<\/li>\n
  • LS TTL technology<\/li>\n
  • 15ns typical propagation delay<\/li>\n
  • Industry-standard 7420 pinout<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • 4-input AND function (NAND + inverter)<\/li>\n
    • Address decoding with 4 conditions<\/li>\n
    • Multi-condition gating<\/li>\n
    • General-purpose logic<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS20N from Texas Instruments contains two independent 4-input positive NAND gates in a 14-pin PDIP package \u2014 essential for implementing wide AND\/NAND logic functions with minimal chip count. Key Specifications Number of Gates 2 (dual 4-input NAND) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V Propagation Delay 15ns typical @ […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7969","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual 4-input NAND gate, LS TTL, 15ns, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":6000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls20.pdf","price":"$0.25 @ 1ku","product_introduction":"The SN74LS20N from Texas Instruments contains two independent 4-input NAND gates in a 14-pin PDIP package. Each gate performs Y = NOT(A AND B AND C AND D); the output is LOW only when ALL four inputs are HIGH. This 4-input NAND is valuable for address decoding and multi-condition gating where four signals must all be HIGH (or a combination of HIGH\/LOW with inverters) to produce an active output. A 4-input AND function is obtained by adding an inverter after the NAND. Without the 7420, implementing a 4-input AND would require cascading two 2-input AND gates (7408) plus an extra gate \u2014 three gates versus one. DeMorgan's theorem shows that a 4-input NAND is also equivalent to NOT-A OR NOT-B OR NOT-C OR NOT-D, making it useful for detecting when ANY input is LOW. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each 4-input NAND gate performs Y = (A \u00b7 B \u00b7 C \u00b7 D)' \u2014 the output is LOW only when all four inputs A, B, C, and D are simultaneously HIGH. If any input is LOW, the output is HIGH. Truth table for one gate: 16 possible input combinations, only one (1111) produces LOW output. The NAND is a universal gate: any Boolean function can be implemented using only NAND gates. For a 4-input AND: Y = (A\u00b7B\u00b7C\u00b7D)'' = A\u00b7B\u00b7C\u00b7D \u2014 add an inverter (7404 or one input of a NAND gate with tied inputs) after the 4-input NAND. For address decoding: if a memory device must be selected when A15=1, A14=1, A13=1, and MREQ=0, connect A15,A14,A13,MREQ' (inverted) to the four inputs; the NAND output goes LOW only when all conditions are met (active-LOW chip select). The 15ns propagation delay means the output responds within 15ns of any input change.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1A<\/td>Input<\/td>Gate 1 input A<\/td><\/tr>\n
      2<\/td>1B<\/td>Input<\/td>Gate 1 input B<\/td><\/tr>\n
      3<\/td>NC<\/td>\u2014<\/td>No connect<\/td><\/tr>\n
      4<\/td>1C<\/td>Input<\/td>Gate 1 input C<\/td><\/tr>\n
      5<\/td>1D<\/td>Input<\/td>Gate 1 input D<\/td><\/tr>\n
      6<\/td>1Y<\/td>Output<\/td>Gate 1 output (NAND)<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>2Y<\/td>Output<\/td>Gate 2 output (NAND)<\/td><\/tr>\n
      9<\/td>2A<\/td>Input<\/td>Gate 2 input A<\/td><\/tr>\n
      10<\/td>2B<\/td>Input<\/td>Gate 2 input B<\/td><\/tr>\n
      11<\/td>NC<\/td>\u2014<\/td>No connect<\/td><\/tr>\n
      12<\/td>2C<\/td>Input<\/td>Gate 2 input C<\/td><\/tr>\n
      13<\/td>2D<\/td>Input<\/td>Gate 2 input D<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>\n

      SN74LS20N uses the PDIP-14 package with standard 74LS TTL pinout: VCC at Pin 14, GND at Pin 7. Each NAND gate has four inputs and one output \u2014 Gate 1: Pins 1-4 (inputs), Pin 6 (output); Gate 2: Pins 9-12 (inputs), Pin 8 (output). Pins 5 and 13 are not connected. The LS technology provides typical propagation delay of 15ns and power dissipation of 2mW per gate. For push-pull active pull-up outputs, use SN74HC20N or SN74HCT20N which maintain the same pinout. The 74ALS20 provides lower power at similar speed as an advanced alternative.<\/p>","application_scenarios":"

        \n
      • 4-Input AND:<\/strong> 4 signals \u2192 7420 NAND \u2192 7404 inverter \u2192 active-HIGH when all 4 inputs are HIGH<\/li>\n
      • Chip Select Decode:<\/strong> A15, A14, A13, MREQ' \u2192 7420 \u2192 active-LOW chip select; LOW only when all 4 are HIGH<\/li>\n
      • Multi-Condition Enable:<\/strong> System OK = PowerGood AND NoFault AND NoOvertemp AND NoAlarm; 4 signals \u2192 NAND \u2192 inverter \u2192 active-HIGH system OK<\/li>\n
      • 5+ Input AND:<\/strong> Combine 7420 output with 5th input in 7400 NAND \u2192 inverter; 5-input AND<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS20N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS20D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC20D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC20N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT20D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT20N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC20D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC20N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC20D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC20N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7420 is a Dual 4-Input NAND Gate. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7969","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7969"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7969\/revisions"}],"predecessor-version":[{"id":8165,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7969\/revisions\/8165"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7969"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7969"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7969"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7969"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}