{"id":7968,"date":"2026-06-28T06:17:36","date_gmt":"2026-06-28T06:17:36","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls194n\/"},"modified":"2026-06-28T11:45:05","modified_gmt":"2026-06-28T11:45:05","slug":"sn74ls194n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls194n\/","title":{"rendered":"SN74LS194N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS194N from Texas Instruments is a 4-bit bidirectional universal shift register with parallel load, serial shift left\/right, and synchronous mode control in a 16-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Funci\u00f3n<\/td>\n4-bit bidirectional universal shift register<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
Modes<\/td>\nInhibit, Shift Right, Shift Left, Parallel Load<\/td>\n<\/tr>\n
Mode Control<\/td>\nS0 and S1 pins (2-bit select)<\/td>\n<\/tr>\n
Serial Inputs<\/td>\nSR SER (shift right), SL SER (shift left)<\/td>\n<\/tr>\n
Parallel Inputs<\/td>\nA, B, C, D<\/td>\n<\/tr>\n
Outputs<\/td>\nQA, QB, QC, QD<\/td>\n<\/tr>\n
Clear<\/td>\nAsynchronous, active LOW<\/td>\n<\/tr>\n
Max Clock Frequency<\/td>\n25MHz typical<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Four operating modes: hold, shift right, shift left, parallel load<\/li>\n
  • Synchronous mode selection via S0, S1<\/li>\n
  • Dedicated serial inputs for left and right shift<\/li>\n
  • Direct overriding clear<\/li>\n
  • Cascadable for wider registers<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Serial-to-parallel and parallel-to-serial conversion<\/li>\n
    • Arithmetic shift (multiply\/divide by 2)<\/li>\n
    • General-purpose data routing<\/li>\n
    • Pseudo-random number generator<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS194N from Texas Instruments is a 4-bit bidirectional universal shift register with parallel load, serial shift left\/right, and synchronous mode control in a 16-pin PDIP package. Key Specifications Function 4-bit bidirectional universal shift register Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V Modes Inhibit, Shift Right, Shift Left, Parallel Load […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7968","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"4-bit bidirectional universal shift register, LS TTL, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":3500,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls194a.pdf","price":"$0.65 @ 1ku","product_introduction":"The SN74LS194N from Texas Instruments is a 4-bit bidirectional universal shift register that can perform four operations: hold (no change), shift right, shift left, and parallel load \u2014 all selected by the 2-bit mode control (S0, S1). On each rising clock edge, the selected operation is performed synchronously. Shift right: QA\u2192QB\u2192QC\u2192QD, with the new QA loaded from SR SER. Shift left: QD\u2192QC\u2192QB\u2192QA, with the new QD loaded from SL SER. Parallel load: A\u2192QA, B\u2192QB, C\u2192QC, D\u2192QD simultaneously. Hold: S0=S1=0, no change on any output. The asynchronous CLR input resets all outputs to 0 regardless of the clock. The 74194 is called 'universal' because it handles all common shift register operations in one IC. Two 74194s cascade to form an 8-bit register: QD of the first connects to SL SER of the second (for left shift), and QA of the second connects to SR SER of the first (for right shift). The N suffix denotes the PDIP-16 package.","working_principle":"The SN74LS194N has four D-type flip-flops (QA-QD) whose D inputs are connected to a 4:1 multiplexer controlled by S0 and S1. The multiplexer selects the source for each flip-flop: (1) S0=0, S1=0: each D input connects to its own Q output \u2192 HOLD (no change). (2) S0=1, S1=0: each D input connects to the previous stage \u2192 SHIFT RIGHT: QA\u2190SR_SER, QB\u2190QA, QC\u2190QB, QD\u2190QC. (3) S0=0, S1=1: each D input connects to the next stage \u2192 SHIFT LEFT: QD\u2190SL_SER, QC\u2190QD, QB\u2190QC, QA\u2190QB. (4) S0=1, S1=1: each D input connects to its parallel input \u2192 PARALLEL LOAD: QA\u2190A, QB\u2190B, QC\u2190C, QD\u2190D. All changes occur on the rising edge of CLK. The CLR input is asynchronous and overrides everything: when CLR=LOW, all Q outputs go LOW immediately. For serial-to-parallel conversion: feed serial data into SR SER, clock 4 times with S0=1,S1=0, then read QA-QD as parallel data. For parallel-to-serial: first parallel load (S0=S1=1), then shift right 4 times, reading QD each time.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>CLR<\/td>Input<\/td>Asynchronous clear (active LOW)<\/td><\/tr>\n
      2<\/td>SR SER<\/td>Input<\/td>Serial shift-right input<\/td><\/tr>\n
      3<\/td>A<\/td>Input<\/td>Parallel input A (QA)<\/td><\/tr>\n
      4<\/td>B<\/td>Input<\/td>Parallel input B (QB)<\/td><\/tr>\n
      5<\/td>C<\/td>Input<\/td>Parallel input C (QC)<\/td><\/tr>\n
      6<\/td>D<\/td>Input<\/td>Parallel input D (QD)<\/td><\/tr>\n
      7<\/td>S1<\/td>Input<\/td>Mode select 1 (with S0: 00=hold, 01=left, 10=right, 11=load)<\/td><\/tr>\n
      8<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>S0<\/td>Input<\/td>Mode select 0<\/td><\/tr>\n
      10<\/td>SL SER<\/td>Input<\/td>Serial shift-left input<\/td><\/tr>\n
      11<\/td>CLK<\/td>Input<\/td>Clock input (rising edge)<\/td><\/tr>\n
      12<\/td>QD<\/td>Output<\/td>Register output D (MSB)<\/td><\/tr>\n
      13<\/td>QC<\/td>Output<\/td>Register output C<\/td><\/tr>\n
      14<\/td>QB<\/td>Output<\/td>Register output B<\/td><\/tr>\n
      15<\/td>QA<\/td>Output<\/td>Register output A (LSB)<\/td><\/tr>\n
      16<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Serial-to-Parallel:<\/strong> Serial data \u2192 SR SER; S0=1,S1=0; clock 4 times; read QA-QD as parallel output<\/li>\n
      • Parallel-to-Serial:<\/strong> Data on A-D; S0=S1=1, clock once to load; then S0=1,S1=0, clock 4 times; read QD each clock for serial out<\/li>\n
      • Multiply by 2:<\/strong> Parallel load number into QA-QD; then shift left once (S0=0,S1=1, clock); result = 2\u00d7 original; shift left again = 4\u00d7<\/li>\n
      • 8-Bit Register:<\/strong> Two 74194; QD(#1)\u2192SL SER(#2); QA(#2)\u2192SR SER(#1); shared CLK, S0, S1, CLR; 8-bit bidirectional shift<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS194N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS194D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC194D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC194N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT194D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT194N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n<\/table>\n

        The 74194 is a 4-Bit Bidirectional Universal Shift Register. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7968","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7968"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7968\/revisions"}],"predecessor-version":[{"id":8166,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7968\/revisions\/8166"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7968"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7968"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7968"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7968"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}