{"id":7932,"date":"2026-06-28T05:53:59","date_gmt":"2026-06-28T05:53:59","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls00n\/"},"modified":"2026-06-28T11:45:50","modified_gmt":"2026-06-28T11:45:50","slug":"sn74ls00n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls00n\/","title":{"rendered":"SN74LS00N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS00N from Texas Instruments is a quad 2-input NAND gate\u2014the most fundamental and widely-used TTL logic IC\u2014with 15ns propagation delay and industry-standard 7400 pinout in a 14-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n
Number of Gates<\/td>\n4 (quad 2-input NAND)<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n15ns typical @ 5V<\/td>\n<\/tr>\n
Output Drive (IOL\/IOH)<\/td>\n8mA \/ -0.4mA<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Four independent 2-input NAND gates<\/li>\n
  • LS TTL technology<\/li>\n
  • 15ns typical propagation delay<\/li>\n
  • Industry-standard 7400 pinout<\/li>\n
  • NAND is a universal logic gate<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • General-purpose logic gating<\/li>\n
    • SR latch construction<\/li>\n
    • Active-low signal combination<\/li>\n
    • Logic function implementation<\/li>\n
    • Glue logic in digital systems<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS00N from Texas Instruments is a quad 2-input NAND gate\u2014the most fundamental and widely-used TTL logic IC\u2014with 15ns propagation delay and industry-standard 7400 pinout in a 14-pin PDIP package. Key Specifications Number of Gates 4 (quad 2-input NAND) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Propagation Delay […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7932","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Quad 2-input NAND gate, LS TTL, 15ns, PDIP-14, universal gate","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":15000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls00.pdf","price":"$0.22 @ 1ku","product_introduction":"The SN74LS00N from Texas Instruments contains four independent 2-input NAND gates in a 14-pin PDIP package\u2014the original and most iconic TTL logic IC. Each gate performs the Boolean function Y = NOT(A AND B); the output is LOW only when both inputs are HIGH. The NAND gate is a universal gate: any Boolean function can be implemented using only NAND gates. An inverter is a NAND with both inputs tied together; an AND is a NAND followed by an inverter (two NANDs); an OR is NAND gates with inverted inputs. Two NAND gates cross-coupled form an SR latch. The 74LS00 is the simplest and most versatile logic building block, found in virtually every digital system from the 1970s to today. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each NAND gate in the SN74LS00N performs Y = A NAND B = NOT(A AND B). The truth table is: 00\u21921, 01\u21921, 10\u21921, 11\u21920. The output is LOW only when ALL inputs are HIGH. As a universal gate, the NAND can implement any Boolean function: NOT(A) = A NAND A; A AND B = NOT(A NAND B) = (A NAND B) NAND (A NAND B); A OR B = (A NAND A) NAND (B NAND B). Two cross-coupled NAND gates form an SR latch: if S goes LOW, Q goes HIGH; if R goes LOW, Q goes LOW. When both S and R are HIGH, the latch holds its previous state. The LS (Low-power Schottky) technology uses Schottky-clamped transistors that prevent deep saturation, providing 15ns propagation delay\u20143\u00d7 faster than standard 7400 TTL\u2014while consuming only about 2mW per gate.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1A<\/td>Input<\/td>Gate 1 input A<\/td><\/tr>\n
      2<\/td>1B<\/td>Input<\/td>Gate 1 input B<\/td><\/tr>\n
      3<\/td>1Y<\/td>Output<\/td>Gate 1 output (NAND)<\/td><\/tr>\n
      4<\/td>2A<\/td>Input<\/td>Gate 2 input A<\/td><\/tr>\n
      5<\/td>2B<\/td>Input<\/td>Gate 2 input B<\/td><\/tr>\n
      6<\/td>2Y<\/td>Output<\/td>Gate 2 output (NAND)<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>3Y<\/td>Output<\/td>Gate 3 output (NAND)<\/td><\/tr>\n
      9<\/td>3A<\/td>Input<\/td>Gate 3 input A<\/td><\/tr>\n
      10<\/td>3B<\/td>Input<\/td>Gate 3 input B<\/td><\/tr>\n
      11<\/td>4Y<\/td>Output<\/td>Gate 4 output (NAND)<\/td><\/tr>\n
      12<\/td>4A<\/td>Input<\/td>Gate 4 input A<\/td><\/tr>\n
      13<\/td>4B<\/td>Input<\/td>Gate 4 input B<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • SR Latch:<\/strong> Two NAND gates cross-coupled; S=LOW sets Q=HIGH; R=LOW resets Q=LOW; simplest memory element<\/li>\n
      • Inverter:<\/strong> Tie both inputs together; NAND(A,A) = NOT(A); saves using a 7404<\/li>\n
      • Active-LOW AND:<\/strong> NAND combines two active-low inputs; output goes HIGH when EITHER input goes LOW<\/li>\n
      • Glue Logic:<\/strong> General-purpose NAND for combinational logic; implements any Boolean function with enough gates<\/li>\n
      • Oscillator:<\/strong> Three NAND gates in a ring (each output to next input) with RC delay; simple clock generator<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS00N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS00D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC00D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC00N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT00D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT00N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC00D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC00N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC00D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC00N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74AUP00D<\/td>TI\/Nexperia<\/td>Ultra-low power CMOS with 0.8-3.6V supply for battery-powered and mobile applications<\/td>SOIC-14<\/td>0.8-3.6V CMOS<\/td><\/tr>\n
        74AUP00N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AUP family for prototyping and repair<\/td>DIP-14<\/td>0.8-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7400 is a Quad 2-Input NAND Gate. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7932","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7932"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7932\/revisions"}],"predecessor-version":[{"id":8186,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7932\/revisions\/8186"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7932"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7932"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7932"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7932"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}