{"id":7927,"date":"2026-06-28T04:28:54","date_gmt":"2026-06-28T04:28:54","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls02n\/"},"modified":"2026-06-28T11:45:55","modified_gmt":"2026-06-28T11:45:55","slug":"sn74ls02n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls02n\/","title":{"rendered":"SN74LS02N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS02N from Texas Instruments is a quad 2-input NOR gate with LS TTL technology, 15ns propagation delay, and industry-standard 7402 pinout in a 14-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n
Number of Gates<\/td>\n4 (quad 2-input NOR)<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n15ns typical @ 5V<\/td>\n<\/tr>\n
Output Drive (IOL\/IOH)<\/td>\n8mA \/ -0.4mA<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Four independent 2-input NOR gates<\/li>\n
  • LS TTL technology<\/li>\n
  • 15ns typical propagation delay<\/li>\n
  • Industry-standard 7402 pinout<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Logic NOR function implementation<\/li>\n
    • Active-low signal OR (negative logic AND)<\/li>\n
    • SR latch construction<\/li>\n
    • Address decoding with active-low outputs<\/li>\n
    • General-purpose logic gating<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS02N from Texas Instruments is a quad 2-input NOR gate with LS TTL technology, 15ns propagation delay, and industry-standard 7402 pinout in a 14-pin PDIP package. Key Specifications Number of Gates 4 (quad 2-input NOR) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Propagation Delay 15ns typical @ […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7927","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Quad 2-input NOR gate, LS TTL, 15ns, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":5500,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls02.pdf","price":"$0.28 @ 1ku","product_introduction":"The SN74LS02N from Texas Instruments contains four independent 2-input NOR gates in a 14-pin PDIP through-hole package. Each gate performs the Boolean function Y = NOT(A OR B); the output is HIGH only when both inputs are LOW. By DeMorgan's theorem, a NOR gate also functions as an AND gate in negative logic: Y = A (negative-AND) B, where the output is LOW when either input is HIGH. This makes NOR gates useful for combining active-low signals such as chip selects and interrupt lines. The NOR gate is also a universal gate: any Boolean function can be implemented using only NOR gates (or only NAND gates). Two NOR gates cross-coupled form an SR latch, the simplest sequential logic element. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each NOR gate in the SN74LS02N performs the Boolean function Y = A NOR B = NOT(A OR B). The output is HIGH only when both inputs are LOW. The truth table is: 00\u21921, 01\u21920, 10\u21920, 11\u21920. By DeMorgan's theorem, A NOR B = NOT(A) AND NOT(B), meaning the NOR gate is equivalent to an AND gate with inverted inputs. This dual interpretation is useful in active-low logic systems common in TTL design. Two NOR gates cross-coupled form a basic SR latch: if S (set) goes HIGH, Q goes HIGH; if R (reset) goes HIGH, Q goes LOW. When both S and R are LOW, the latch holds its previous state. The NOR gate is a universal gate: an inverter is a NOR gate with both inputs tied together; an OR gate is a NOR gate followed by an inverter; an AND gate is a NOR gate with inverted inputs (which are themselves NOR-based inverters).","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1Y<\/td>Output<\/td>Gate 1 output (NOR)<\/td><\/tr>\n
      2<\/td>1A<\/td>Input<\/td>Gate 1 input A<\/td><\/tr>\n
      3<\/td>1B<\/td>Input<\/td>Gate 1 input B<\/td><\/tr>\n
      4<\/td>2Y<\/td>Output<\/td>Gate 2 output (NOR)<\/td><\/tr>\n
      5<\/td>2A<\/td>Input<\/td>Gate 2 input A<\/td><\/tr>\n
      6<\/td>2B<\/td>Input<\/td>Gate 2 input B<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>3A<\/td>Input<\/td>Gate 3 input A<\/td><\/tr>\n
      9<\/td>3B<\/td>Input<\/td>Gate 3 input B<\/td><\/tr>\n
      10<\/td>3Y<\/td>Output<\/td>Gate 3 output (NOR)<\/td><\/tr>\n
      11<\/td>4A<\/td>Input<\/td>Gate 4 input A<\/td><\/tr>\n
      12<\/td>4B<\/td>Input<\/td>Gate 4 input B<\/td><\/tr>\n
      13<\/td>4Y<\/td>Output<\/td>Gate 4 output (NOR)<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • SR Latch:<\/strong> Two NOR gates cross-coupled; S=HIGH sets Q=HIGH; R=HIGH resets Q=LOW; basic memory element<\/li>\n
      • Active-Low OR:<\/strong> Two active-low enables NORed; output goes HIGH only when BOTH enables are inactive (deasserted)<\/li>\n
      • Power-On Reset:<\/strong> RC on one input; other input HIGH; output HIGH during power-up, LOW after cap charges<\/li>\n
      • Decoder:<\/strong> NOR of decoded address bits; output HIGH only when all address bits are LOW (specific address)<\/li>\n
      • Inverter:<\/strong> Tie both inputs together; NOR(A, A) = NOT(A); saves using a 7404 inverter<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS02N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS02D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC02D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC02N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT02D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT02N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC02D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC02N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC02D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC02N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7402 is a Quad 2-Input NOR Gate. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7927","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7927"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7927\/revisions"}],"predecessor-version":[{"id":8187,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7927\/revisions\/8187"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7927"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7927"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7927"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7927"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}