{"id":7925,"date":"2026-06-28T04:28:52","date_gmt":"2026-06-28T04:28:52","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls175n\/"},"modified":"2026-06-28T11:45:58","modified_gmt":"2026-06-28T11:45:58","slug":"sn74ls175n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls175n\/","title":{"rendered":"SN74LS175N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS175N from Texas Instruments is a quad D-type flip-flop with complementary outputs, common clock and clear inputs, and edge-triggered operation in a 16-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Number of Flip-Flops<\/td>\n4 (quad D-type)<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
Trigger Type<\/td>\nPositive-edge triggered (rising edge of CLK)<\/td>\n<\/tr>\n
Outputs<\/td>\nTrue (Q) and complementary (Q\u0305) per flip-flop<\/td>\n<\/tr>\n
Propagation Delay (CLK to Q)<\/td>\n25ns typical<\/td>\n<\/tr>\n
Maximum Clock Frequency<\/td>\n30MHz typical<\/td>\n<\/tr>\n
Setup Time<\/td>\n15ns minimum before clock edge<\/td>\n<\/tr>\n
Hold Time<\/td>\n0ns minimum after clock edge<\/td>\n<\/tr>\n
Clear (CLR)<\/td>\nActive-low, asynchronous, overrides all<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Four D-type edge-triggered flip-flops<\/li>\n
  • Complementary outputs (Q and Q\u0305)<\/li>\n
  • Common clock input for all four flip-flops<\/li>\n
  • Asynchronous clear (active-low)<\/li>\n
  • 30MHz maximum clock frequency<\/li>\n
  • Zero hold time simplifies design<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Parallel data register<\/li>\n
    • Data synchronization and capture<\/li>\n
    • Address latching<\/li>\n
    • Frequency division<\/li>\n
    • Digital delay elements<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS175N from Texas Instruments is a quad D-type flip-flop with complementary outputs, common clock and clear inputs, and edge-triggered operation in a 16-pin PDIP package. Key Specifications Number of Flip-Flops 4 (quad D-type) Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Trigger Type Positive-edge triggered (rising edge of […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7925","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Quad D flip-flop, edge-triggered, Q+Q\u0305, common CLK\/CLR, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":4200,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls175.pdf","price":"$0.48 @ 1ku","product_introduction":"The SN74LS175N from Texas Instruments contains four D-type positive-edge-triggered flip-flops with a common clock (CLK) and common asynchronous clear (CLR) input. Each flip-flop has both true (Q) and complementary (Q\u0305) outputs. On the rising edge of CLK, the data at each D input is transferred to the corresponding Q output. The asynchronous CLR input, when LOW, immediately resets all Q outputs to LOW regardless of the clock or D inputs. The complementary outputs are useful for generating both active-HIGH and active-LOW versions of a stored signal without additional inverters. The 30MHz maximum clock frequency and 15ns setup time make it suitable for moderate-speed digital systems. The zero hold time simplifies cascading with other TTL logic. The N suffix denotes the PDIP-16 through-hole package.","working_principle":"Each of the four D-type flip-flops in the SN74LS175N captures the logic level at its D input on the rising edge of the common CLK signal. The captured value appears at the Q output, and the inverted value appears at the Q\u0305 output. Between clock edges, the outputs hold their previous values regardless of changes on the D inputs. The setup time requirement (15ns minimum) means the D input must be stable for at least 15ns before the clock edge for reliable capture. The zero hold time means the D input can change immediately after the clock edge without risk of metastability. The asynchronous clear (CLR) overrides everything: when CLR goes LOW, all Q outputs immediately go LOW, regardless of CLK or D. When CLR is HIGH, the flip-flops operate normally on clock edges. In a parallel data register application, four data bits are presented to the D inputs, and a single clock edge captures all four simultaneously. This is useful for sampling a parallel bus, synchronizing asynchronous inputs to the system clock, or creating a pipeline stage.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>CLR<\/td>Input<\/td>Asynchronous clear (active LOW, resets all Q to LOW)<\/td><\/tr>\n
      2<\/td>1Q<\/td>Output<\/td>Flip-flop 1 true output<\/td><\/tr>\n
      3<\/td>1Q\u0305<\/td>Output<\/td>Flip-flop 1 complementary output<\/td><\/tr>\n
      4<\/td>1D<\/td>Input<\/td>Flip-flop 1 data input<\/td><\/tr>\n
      5<\/td>2D<\/td>Input<\/td>Flip-flop 2 data input<\/td><\/tr>\n
      6<\/td>2Q\u0305<\/td>Output<\/td>Flip-flop 2 complementary output<\/td><\/tr>\n
      7<\/td>2Q<\/td>Output<\/td>Flip-flop 2 true output<\/td><\/tr>\n
      8<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>CLK<\/td>Input<\/td>Clock (rising edge triggers data capture)<\/td><\/tr>\n
      10<\/td>3Q<\/td>Output<\/td>Flip-flop 3 true output<\/td><\/tr>\n
      11<\/td>3Q\u0305<\/td>Output<\/td>Flip-flop 3 complementary output<\/td><\/tr>\n
      12<\/td>3D<\/td>Input<\/td>Flip-flop 3 data input<\/td><\/tr>\n
      13<\/td>4D<\/td>Input<\/td>Flip-flop 4 data input<\/td><\/tr>\n
      14<\/td>4Q\u0305<\/td>Output<\/td>Flip-flop 4 complementary output<\/td><\/tr>\n
      15<\/td>4Q<\/td>Output<\/td>Flip-flop 4 true output<\/td><\/tr>\n
      16<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Parallel Register:<\/strong> 4-bit data bus \u2192 D inputs; CLK edge captures all 4 bits simultaneously; Q outputs hold data for downstream logic<\/li>\n
      • Synchronizer:<\/strong> Asynchronous inputs \u2192 D; CLK = system clock; Q outputs are synchronous to clock domain<\/li>\n
      • Address Latch:<\/strong> Multiplexed address\/data bus \u2192 D; ALE signal \u2192 CLK; Q holds address during data phase<\/li>\n
      • Frequency \u00f72:<\/strong> Connect Q\u0305 to D; CLK input = input frequency; Q output = half frequency (toggle mode)<\/li>\n
      • Digital Delay:<\/strong> Chain of 175s; data passes through each register on successive clock edges; 4-clock delay per stage<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS175N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS175D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC175D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC175N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT175D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT175N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74LVC175D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-16<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC175N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-16<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 74175 is a Quad D-Type Flip-Flop with Clear. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7925","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7925"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7925\/revisions"}],"predecessor-version":[{"id":8189,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7925\/revisions\/8189"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7925"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7925"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7925"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7925"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}