{"id":7905,"date":"2026-06-28T03:26:51","date_gmt":"2026-06-28T03:26:51","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls373n\/"},"modified":"2026-06-28T11:46:20","modified_gmt":"2026-06-28T11:46:20","slug":"sn74ls373n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls373n\/","title":{"rendered":"SN74LS373N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS373N is an octal transparent D-type latch with 3-state outputs from Texas Instruments, featuring separate output enable and latch enable controls in a 20-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n
Number of Bits<\/td>\n8 (octal)<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Funci\u00f3n<\/td>\nTransparent D-type latch<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
Propagation Delay (D to Q)<\/td>\n18ns typical<\/td>\n<\/tr>\n
Latch Enable to Output<\/td>\n27ns typical<\/td>\n<\/tr>\n
Output Type<\/td>\n3-state (high-impedance when disabled)<\/td>\n<\/tr>\n
Output Enable (OE)<\/td>\nActive-low (single pin controls all 8 outputs)<\/td>\n<\/tr>\n
Output Drive (IOL\/IOH)<\/td>\n24mA \/ -2.6mA<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-20 (24.33 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • 8-bit transparent latch with 3-state outputs<\/li>\n
  • Single latch enable (LE) controls all 8 latches<\/li>\n
  • Single output enable (OE) controls all 8 outputs<\/li>\n
  • When LE is HIGH, outputs follow inputs (transparent)<\/li>\n
  • When LE goes LOW, data is latched and held<\/li>\n
  • 3-state outputs for bus-oriented applications<\/li>\n
  • Direct replacement for 74LS373 from any manufacturer<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Microprocessor address latch<\/li>\n
    • Data register and hold register<\/li>\n
    • Bus buffer and isolation<\/li>\n
    • I\/O port output register<\/li>\n
    • Demultiplexed bus systems<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS373N is an octal transparent D-type latch with 3-state outputs from Texas Instruments, featuring separate output enable and latch enable controls in a 20-pin PDIP package. Key Specifications Number of Bits 8 (octal) Logic Family LS (Low-power Schottky) Function Transparent D-type latch Supply Voltage 4.75V to 5.25V (5V nominal) Propagation Delay (D […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7905","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Octal transparent D-latch, 3-state out, single LE\/OE, LS TTL, PDIP-20","date_code":"","package_case":"PDIP-20 (24.33 x 6.35 x 5.08mm, 2.54mm pitch, through-hole)","in_stock":8000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls373.pdf","price":"$0.52 @ 1ku","product_introduction":"The SN74LS373N from Texas Instruments is an 8-bit transparent D-type latch with 3-state outputs, designed for bus-oriented applications in microprocessor and digital systems. When the Latch Enable (LE) input is HIGH, the latch is transparent\u2014each output (Q) follows its corresponding data input (D). When LE transitions LOW, the data present at the inputs is latched and held at the outputs, regardless of subsequent input changes. The Output Enable (OE) input, when LOW, enables the 3-state output drivers; when OE is HIGH, all outputs enter the high-impedance state, effectively disconnecting the latch from the bus. This allows multiple SN74LS373 devices to share a common data bus. The device is commonly used in 8051 and similar microprocessor systems to demultiplex the address\/data bus by latching the address on the falling edge of ALE. The N suffix denotes the PDIP-20 through-hole package.","working_principle":"The SN74LS373N contains eight identical D-type transparent latches with common control inputs. Each latch has a data input (D) and a 3-state output (Q). When LE is HIGH, the latch is transparent: Q follows D with an 18ns propagation delay. This means the latch acts as a wire\u2014data passes through unimpeded. When LE transitions from HIGH to LOW, the current D value is captured and held on Q. Subsequent changes on D are ignored until LE goes HIGH again. The OE control is independent of LE. When OE is LOW, the 3-state output buffers are active and Q drives the bus. When OE is HIGH, the output buffers enter the high-impedance state (both pull-up and pull-up transistors OFF), regardless of the latched data. This allows multiple 373 devices to share the same bus\u2014only one should have OE LOW at a time. The typical application in 8051 systems: the multiplexed AD0-AD7 bus connects to the D inputs; the ALE signal connects to LE. During the address phase, ALE is HIGH and the address flows through to Q. When ALE falls, the address is latched. The bus then switches to data, but the latched address remains on Q for the duration of the bus cycle.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>OE<\/td>Input<\/td>Output enable (active low, 3-state control)<\/td><\/tr>\n
      2<\/td>1Q<\/td>Output<\/td>Latch 1 output (3-state)<\/td><\/tr>\n
      3<\/td>1D<\/td>Input<\/td>Latch 1 data input<\/td><\/tr>\n
      4<\/td>2D<\/td>Input<\/td>Latch 2 data input<\/td><\/tr>\n
      5<\/td>2Q<\/td>Output<\/td>Latch 2 output (3-state)<\/td><\/tr>\n
      6<\/td>3Q<\/td>Output<\/td>Latch 3 output (3-state)<\/td><\/tr>\n
      7<\/td>3D<\/td>Input<\/td>Latch 3 data input<\/td><\/tr>\n
      8<\/td>4D<\/td>Input<\/td>Latch 4 data input<\/td><\/tr>\n
      9<\/td>4Q<\/td>Output<\/td>Latch 4 output (3-state)<\/td><\/tr>\n
      10<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      11<\/td>LE<\/td>Input<\/td>Latch enable (HIGH=transparent, LOW=latched)<\/td><\/tr>\n
      12<\/td>5Q<\/td>Output<\/td>Latch 5 output (3-state)<\/td><\/tr>\n
      13<\/td>5D<\/td>Input<\/td>Latch 5 data input<\/td><\/tr>\n
      14<\/td>6D<\/td>Input<\/td>Latch 6 data input<\/td><\/tr>\n
      15<\/td>6Q<\/td>Output<\/td>Latch 6 output (3-state)<\/td><\/tr>\n
      16<\/td>7Q<\/td>Output<\/td>Latch 7 output (3-state)<\/td><\/tr>\n
      17<\/td>7D<\/td>Input<\/td>Latch 7 data input<\/td><\/tr>\n
      18<\/td>8D<\/td>Input<\/td>Latch 8 data input<\/td><\/tr>\n
      19<\/td>8Q<\/td>Output<\/td>Latch 8 output (3-state)<\/td><\/tr>\n
      20<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Mux Bus Demux:<\/strong> 8051 ALE signal latches lower address byte from multiplexed AD0-AD7 bus<\/li>\n
      • Output Register:<\/strong> Write data to latch, disable LE; data holds on outputs until next write<\/li>\n
      • Bus Isolation:<\/strong> OE=HIGH disconnects latch from shared bus; OE=LOW when this device drives the bus<\/li>\n
      • Input Port:<\/strong> External signals pass through transparent latch when LE=HIGH; latch on LE=LOW to freeze during read<\/li>\n
      • Pipeline Stage:<\/strong> LE strobes at each clock phase to create an 8-bit pipeline register<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS373N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-20<\/td>5V TTL<\/td><\/tr>\n
        74LS373D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-20<\/td>5V TTL<\/td><\/tr>\n
        74HC373D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-20<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC373N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-20<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT373D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-20<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT373N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-20<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74LVC373D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-20<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC373N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-20<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 74373 is a Octal Transparent Latch with 3-State Output. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7905","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7905"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7905\/revisions"}],"predecessor-version":[{"id":8198,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7905\/revisions\/8198"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7905"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7905"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7905"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7905"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}