{"id":7904,"date":"2026-06-28T03:26:50","date_gmt":"2026-06-28T03:26:50","guid":{"rendered":"https:\/\/materialparts.com\/sn74hc00n\/"},"modified":"2026-06-28T11:46:21","modified_gmt":"2026-06-28T11:46:21","slug":"sn74hc00n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74hc00n\/","title":{"rendered":"SN74HC00N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74HC00N is a quad 2-input NAND gate from Texas Instruments with HC CMOS technology, wide voltage range (2V to 6V), and 10ns propagation delay in a 14-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n
Number of Gates<\/td>\n4 (quad 2-input NAND)<\/td>\n<\/tr>\n
Logic Family<\/td>\nHC (High-speed CMOS)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n2V to 6V<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n10ns typical @ 5V<\/td>\n<\/tr>\n
Output Drive Current<\/td>\n\u00b14mA @ 5V (symmetric)<\/td>\n<\/tr>\n
Input Level<\/td>\nCMOS<\/td>\n<\/tr>\n
Quiescent Supply Current<\/td>\n2\u00b5A max @ 5V<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n-40\u00b0C to +85\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Four independent 2-input NAND gates<\/li>\n
  • Wide supply voltage: 2V to 6V<\/li>\n
  • HC CMOS low power: 2\u00b5A max quiescent<\/li>\n
  • Symmetric output drive: \u00b14mA at 5V<\/li>\n
  • 10ns propagation delay at 5V<\/li>\n
  • NAND is universal gate (can build any logic function)<\/li>\n
  • Industry-standard 7400 pinout<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • General-purpose logic gating<\/li>\n
    • Set-reset latches and flip-flops<\/li>\n
    • Logic function construction<\/li>\n
    • Gate enable and chip select logic<\/li>\n
    • Simple oscillators and pulse generators<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74HC00N is a quad 2-input NAND gate from Texas Instruments with HC CMOS technology, wide voltage range (2V to 6V), and 10ns propagation delay in a 14-pin PDIP package. Key Specifications Number of Gates 4 (quad 2-input NAND) Logic Family HC (High-speed CMOS) Supply Voltage 2V to 6V Propagation Delay 10ns typical […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7904","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Quad 2-input NAND gate, HC CMOS 2-6V, 10ns, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":18000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74hc00.pdf","price":"$0.25 @ 1ku","product_introduction":"The SN74HC00N from Texas Instruments contains four independent 2-input NAND gates in a 14-pin PDIP through-hole package. The NAND gate is the universal logic element\u2014all other logic functions (AND, OR, NOT, XOR, etc.) can be constructed using only NAND gates. The HC (High-speed CMOS) technology provides a wide 2V to 6V operating range with extremely low 2\u00b5A quiescent current, making it suitable for both 3.3V and 5V systems. The symmetric \u00b14mA output drive at 5V can source and sink equal current, unlike older TTL devices that had asymmetric drive. The 10ns propagation delay supports clock rates up to 50MHz. The N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each of the four NAND gates in the SN74HC00N performs the Boolean function Y = NOT(A AND B). The output is LOW only when both inputs A and B are HIGH; for all other input combinations (00, 01, 10), the output is HIGH. Because NAND is a functionally complete (universal) gate, any combinational or sequential logic circuit can be implemented using only NAND gates. A NOT gate is formed by tying both inputs together. An AND gate is formed by a NAND followed by a NOT (two NAND gates). An OR gate is formed by inverting both inputs, then NANDing them (three NAND gates). An SR latch is formed by cross-connecting two NAND gates (active-LOW set and reset inputs). The HC CMOS implementation uses complementary NMOS\/PMOS transistors for both pull-up and pull-down, providing symmetric drive capability and rail-to-rail output swing.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1A<\/td>Input<\/td>Gate 1 input A<\/td><\/tr>\n
      2<\/td>1B<\/td>Input<\/td>Gate 1 input B<\/td><\/tr>\n
      3<\/td>1Y<\/td>Output<\/td>Gate 1 output (NAND)<\/td><\/tr>\n
      4<\/td>2A<\/td>Input<\/td>Gate 2 input A<\/td><\/tr>\n
      5<\/td>2B<\/td>Input<\/td>Gate 2 input B<\/td><\/tr>\n
      6<\/td>2Y<\/td>Output<\/td>Gate 2 output (NAND)<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>3Y<\/td>Output<\/td>Gate 3 output (NAND)<\/td><\/tr>\n
      9<\/td>3A<\/td>Input<\/td>Gate 3 input A<\/td><\/tr>\n
      10<\/td>3B<\/td>Input<\/td>Gate 3 input B<\/td><\/tr>\n
      11<\/td>4Y<\/td>Output<\/td>Gate 4 output (NAND)<\/td><\/tr>\n
      12<\/td>4A<\/td>Input<\/td>Gate 4 input A<\/td><\/tr>\n
      13<\/td>4B<\/td>Input<\/td>Gate 4 input B<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (2V to 6V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • SR Latch:<\/strong> Two cross-connected NAND gates create a set-reset latch for debouncing switches<\/li>\n
      • Gate Logic:<\/strong> NAND is universal\u2014build AND, OR, NOT, XOR from combinations of NAND gates<\/li>\n
      • Enable Gate:<\/strong> One input as data, other as enable; when enable=LOW, output is always HIGH (pass-through disabled)<\/li>\n
      • Oscillator:<\/strong> Three NAND gates in a ring with RC feedback create a simple square-wave oscillator<\/li>\n
      • Level Translation:<\/strong> 2V-6V range allows interfacing between 3.3V and 5V logic domains<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS00N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS00D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC00D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC00N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT00D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT00N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC00D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC00N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC00D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC00N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74AUP00D<\/td>TI\/Nexperia<\/td>Ultra-low power CMOS with 0.8-3.6V supply for battery-powered and mobile applications<\/td>SOIC-14<\/td>0.8-3.6V CMOS<\/td><\/tr>\n
        74AUP00N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AUP family for prototyping and repair<\/td>DIP-14<\/td>0.8-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7400 is a Quad 2-Input NAND Gate. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7904","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7904"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7904\/revisions"}],"predecessor-version":[{"id":8199,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7904\/revisions\/8199"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7904"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7904"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7904"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7904"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}