{"id":7896,"date":"2026-06-28T03:21:05","date_gmt":"2026-06-28T03:21:05","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls74an\/"},"modified":"2026-06-28T11:46:31","modified_gmt":"2026-06-28T11:46:31","slug":"sn74ls74an","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls74an\/","title":{"rendered":"SN74LS74AN"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS74AN is a dual positive-edge-triggered D-type flip-flop from Texas Instruments with preset, clear, and complementary outputs in a 14-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Number of Flip-Flops<\/td>\n2 (dual)<\/td>\n<\/tr>\n
Trigger Type<\/td>\nPositive-edge-triggered<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
Max Clock Frequency<\/td>\n25MHz typical<\/td>\n<\/tr>\n
Propagation Delay (CLK to Q)<\/td>\n25ns typical<\/td>\n<\/tr>\n
Preset (Active Low)<\/td>\nYes (asynchronous, sets Q=HIGH)<\/td>\n<\/tr>\n
Clear (Active Low)<\/td>\nYes (asynchronous, sets Q=LOW)<\/td>\n<\/tr>\n
Outputs<\/td>\nQ and Q-bar (complementary)<\/td>\n<\/tr>\n
Output Current (IOL)<\/td>\n8mA<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Dual independent D flip-flops in one package<\/li>\n
  • Positive-edge-triggered clock<\/li>\n
  • Asynchronous preset (active low) and clear (active low)<\/li>\n
  • Complementary Q and Q-bar outputs<\/li>\n
  • Direct replacement for 7474 and 74LS74<\/li>\n
  • Input clamp diodes for undershoot protection<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Frequency division and counters<\/li>\n
    • Data synchronization and storage<\/li>\n
    • Shift register construction<\/li>\n
    • One-shot and toggle circuits<\/li>\n
    • Control state machines<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS74AN is a dual positive-edge-triggered D-type flip-flop from Texas Instruments with preset, clear, and complementary outputs in a 14-pin PDIP package. Key Specifications Number of Flip-Flops 2 (dual) Trigger Type Positive-edge-triggered Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Max Clock Frequency 25MHz typical Propagation Delay (CLK to […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7896","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual D flip-flop, edge-triggered, preset\/clear, LS TTL, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":11000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls74a.pdf","price":"$0.38 @ 1ku","product_introduction":"The SN74LS74AN from Texas Instruments contains two independent positive-edge-triggered D-type flip-flops with asynchronous preset and clear inputs in a 14-pin PDIP through-hole package. Each flip-flop transfers the logic level at the D input to the Q output on the rising edge of the clock (CLK). The asynchronous preset (PRE, active low) forces Q HIGH regardless of the clock or D input. The asynchronous clear (CLR, active low) forces Q LOW regardless of the clock or D input. Both PRE and CLR override the clock, and applying both simultaneously is prohibited (Q and Q-bar would both be HIGH). The complementary outputs (Q and Q-bar) provide both true and inverted data. The device is a direct replacement for the classic 7474 and 74LS74 from any manufacturer. The AN suffix denotes the improved LS version in the PDIP-14 package.","working_principle":"Each D flip-flop in the SN74LS74AN captures the logic state present at its D input on the rising edge of the CLK signal. When CLK transitions from LOW to HIGH, the D input value is latched and appears at the Q output after the propagation delay (25ns typical). The Q-bar output provides the complement. If D is HIGH at the clock edge, Q goes HIGH; if D is LOW, Q goes LOW. The D input must be stable for a setup time (typically 15ns) before the clock edge and held for a hold time (typically 0ns) after the edge. The asynchronous PRE input, when pulled LOW, immediately forces Q HIGH (and Q-bar LOW) regardless of the CLK and D states. Similarly, the CLR input, when pulled LOW, forces Q LOW (and Q-bar HIGH). These asynchronous inputs are level-sensitive and override the synchronous (clocked) operation. When both PRE and CLR are HIGH (inactive), the flip-flop operates in the normal clocked mode. The flip-flop can be wired as a toggle (divide-by-2) by connecting Q-bar to D; each clock edge then toggles the output, dividing the clock frequency by two.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1CLR<\/td>Input<\/td>Flip-flop 1 clear (active low, async)<\/td><\/tr>\n
      2<\/td>1D<\/td>Input<\/td>Flip-flop 1 data input<\/td><\/tr>\n
      3<\/td>1CLK<\/td>Input<\/td>Flip-flop 1 clock (rising edge triggered)<\/td><\/tr>\n
      4<\/td>1PRE<\/td>Input<\/td>Flip-flop 1 preset (active low, async)<\/td><\/tr>\n
      5<\/td>1Q<\/td>Output<\/td>Flip-flop 1 true output<\/td><\/tr>\n
      6<\/td>1Q-bar<\/td>Output<\/td>Flip-flop 1 complement output<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>2Q-bar<\/td>Output<\/td>Flip-flop 2 complement output<\/td><\/tr>\n
      9<\/td>2Q<\/td>Output<\/td>Flip-flop 2 true output<\/td><\/tr>\n
      10<\/td>2PRE<\/td>Input<\/td>Flip-flop 2 preset (active low, async)<\/td><\/tr>\n
      11<\/td>2CLK<\/td>Input<\/td>Flip-flop 2 clock (rising edge triggered)<\/td><\/tr>\n
      12<\/td>2D<\/td>Input<\/td>Flip-flop 2 data input<\/td><\/tr>\n
      13<\/td>2CLR<\/td>Input<\/td>Flip-flop 2 clear (active low, async)<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Frequency Divider:<\/strong> Connect Q-bar to D for divide-by-2; cascade for binary counters (\u00f74, \u00f78, etc.)<\/li>\n
      • Data Sync:<\/strong> Capture asynchronous input on clock edge to synchronize to system clock domain<\/li>\n
      • Shift Register:<\/strong> Chain D-to-Q connections for serial-to-parallel conversion or delay lines<\/li>\n
      • State Machine:<\/strong> Q and Q-bar outputs provide current and complement states for Moore\/Mealy FSM<\/li>\n
      • One-Shot:<\/strong> D tied HIGH with CLK as trigger creates a pulse-width set by external clear timing<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS74N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS74D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC74D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT74D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC74D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC74D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7474 is a Dual D-Type Positive-Edge-Triggered Flip-Flop. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7896","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7896"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7896\/revisions"}],"predecessor-version":[{"id":8202,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7896\/revisions\/8202"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7896"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7896"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7896"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7896"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}