{"id":7894,"date":"2026-06-28T03:21:03","date_gmt":"2026-06-28T03:21:03","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls138n-2\/"},"modified":"2026-06-28T11:46:33","modified_gmt":"2026-06-28T11:46:33","slug":"sn74ls138n-2","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74ls138n-2\/","title":{"rendered":"SN74LS138N"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LS138N is a 3-line to 8-line decoder\/demultiplexer from Texas Instruments with 3 enable inputs and inverting outputs in a 16-pin PDIP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n
Funci\u00f3n<\/td>\n3-to-8 decoder\/demultiplexer<\/td>\n<\/tr>\n
Logic Family<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n4.75V to 5.25V (5V nominal)<\/td>\n<\/tr>\n
Inputs<\/td>\n3 address (A, B, C) + 3 enable (G1, G2A, G2B)<\/td>\n<\/tr>\n
Outputs<\/td>\n8 active-low (Y0-Y7)<\/td>\n<\/tr>\n
Retardo de propagaci\u00f3n<\/td>\n22ns typical (address to output)<\/td>\n<\/tr>\n
Enable to Output Delay<\/td>\n18ns typical<\/td>\n<\/tr>\n
Output Low Current (IOL)<\/td>\n8mA<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
Paquete<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • 3-to-8 line decoder with active-low outputs<\/li>\n
  • 3 enable inputs: G1 (active high), G2A and G2B (active low)<\/li>\n
  • Demultiplexing capability with data input via enable pins<\/li>\n
  • Direct replacement for 74138 and 74LS138<\/li>\n
  • Input clamp diodes for undershoot protection<\/li>\n
  • Multiplex expansion using multiple devices<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Memory chip select decoding<\/li>\n
    • I\/O port address decoding<\/li>\n
    • Data demultiplexing<\/li>\n
    • Clock distribution and enable generation<\/li>\n
    • 7-segment display digit selection<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS138N is a 3-line to 8-line decoder\/demultiplexer from Texas Instruments with 3 enable inputs and inverting outputs in a 16-pin PDIP package. Key Specifications Function 3-to-8 decoder\/demultiplexer Logic Family LS (Low-power Schottky) Supply Voltage 4.75V to 5.25V (5V nominal) Inputs 3 address (A, B, C) + 3 enable (G1, G2A, G2B) Outputs […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7894","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"3-to-8 decoder\/demux, active-low outputs, 3 enables, LS TTL, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":14000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls138.pdf","price":"$0.42 @ 1ku","product_introduction":"The SN74LS138N from Texas Instruments is a 3-line to 8-line decoder\/demultiplexer designed for high-performance memory decoding and data routing. Three binary address inputs (A, B, C) select one of eight active-low outputs (Y0-Y7). The three enable inputs provide flexible control: G1 is active-high, while G2A and G2B are active-low. The device is enabled only when G1 is high AND both G2A and G2B are low. When disabled, all outputs are high (inactive). The active-low outputs directly drive chip-select pins on memory and peripheral ICs without external inverters. As a demultiplexer, data applied to one of the enable inputs is routed to the selected output. Multiple SN74LS138 devices can be cascaded using the enable inputs to expand the decoding range to 4-to-16, 5-to-32, or more. The N suffix denotes the PDIP-16 through-hole package.","working_principle":"The SN74LS138N decodes a 3-bit binary address into one of eight mutually exclusive active-low outputs. When the device is enabled (G1=HIGH, G2A=LOW, G2B=LOW), the 3-bit address on inputs C, B, A (where C is MSB) selects one output to go LOW while all other outputs remain HIGH. For example, CBA=000 selects Y0 (LOW), CBA=001 selects Y1 (LOW), and so on through CBA=111 selecting Y7 (LOW). The three enable inputs provide cascading capability: a 4-to-16 decoder is built by using the 4th address bit to enable one of two 138 devices (G1 of one device, G2A of the other). For demultiplexing, data is applied to one of the enable pins (e.g., G1) while the other enables are held active; the data signal is then routed to the output selected by the address inputs. The active-low output convention matches the active-low chip-select pins found on most memory and peripheral ICs.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>A<\/td>Input<\/td>Address input A (LSB)<\/td><\/tr>\n
      2<\/td>B<\/td>Input<\/td>Address input B<\/td><\/tr>\n
      3<\/td>C<\/td>Input<\/td>Address input C (MSB)<\/td><\/tr>\n
      4<\/td>G2B<\/td>Input<\/td>Enable input (active low)<\/td><\/tr>\n
      5<\/td>G2A<\/td>Input<\/td>Enable input (active low)<\/td><\/tr>\n
      6<\/td>G1<\/td>Input<\/td>Enable input (active high)<\/td><\/tr>\n
      7<\/td>Y7<\/td>Output<\/td>Decoded output 7 (active low)<\/td><\/tr>\n
      8<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>Y6<\/td>Output<\/td>Decoded output 6 (active low)<\/td><\/tr>\n
      10<\/td>Y5<\/td>Output<\/td>Decoded output 5 (active low)<\/td><\/tr>\n
      11<\/td>Y4<\/td>Output<\/td>Decoded output 4 (active low)<\/td><\/tr>\n
      12<\/td>Y3<\/td>Output<\/td>Decoded output 3 (active low)<\/td><\/tr>\n
      13<\/td>Y2<\/td>Output<\/td>Decoded output 2 (active low)<\/td><\/tr>\n
      14<\/td>Y1<\/td>Output<\/td>Decoded output 1 (active low)<\/td><\/tr>\n
      15<\/td>Y0<\/td>Output<\/td>Decoded output 0 (active low)<\/td><\/tr>\n
      16<\/td>VCC<\/td>Power<\/td>Supply (4.75V to 5.25V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Memory Decode:<\/strong> 3 address lines generate 8 active-low chip selects for 8 memory-mapped peripherals<\/li>\n
      • I\/O Port Decode:<\/strong> Cascading two 138s creates a 4-to-16 decoder for 16 I\/O ports from 4 address lines<\/li>\n
      • Display Select:<\/strong> Active-low outputs directly drive common-cathode 7-segment display digit enables<\/li>\n
      • Data Routing:<\/strong> As demultiplexer, routes serial data to one of 8 output destinations under address control<\/li>\n
      • Clock Distribution:<\/strong> Routes a clock signal to one of 8 destinations using enable pin as data input<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS138N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS138D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC138D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC138N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT138D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT138N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC138D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC138N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC138D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-16<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC138N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-16<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 74138 is a 3-Line to 8-Line Decoder\/Demultiplexer. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7894","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7894"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7894\/revisions"}],"predecessor-version":[{"id":8203,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7894\/revisions\/8203"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7894"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7894"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7894"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7894"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}