{"id":7468,"date":"2026-06-24T07:10:07","date_gmt":"2026-06-24T07:10:07","guid":{"rendered":"https:\/\/materialparts.com\/xcf04svog20c\/"},"modified":"2026-06-24T07:10:07","modified_gmt":"2026-06-24T07:10:07","slug":"xcf04svog20c","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/xcf04svog20c\/","title":{"rendered":"XCF04SVOG20C"},"content":{"rendered":"

Productos<\/h2>\n

The XCF04SVOG20C from AMD\/Xilinx is a 4Mbit in-system programmable Platform Flash configuration PROM for Xilinx FPGAs. Supporting serial configuration modes at up to 33MHz with JTAG programming interface, it stores and loads FPGA bitstreams in a compact TSSOP-20 package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n
Densidad<\/td>\n4 Mbit (512 KB)<\/td>\n<\/tr>\n
Supply Voltage (VCCINT)<\/td>\n3.3V<\/td>\n<\/tr>\n
I\/O Voltage (VCCO)<\/td>\n1.8V to 3.3V<\/td>\n<\/tr>\n
Configuration Modes<\/td>\nMaster\/Slave Serial<\/td>\n<\/tr>\n
Max Clock Rate<\/td>\n33 MHz (serial)<\/td>\n<\/tr>\n
Programming Interface<\/td>\nJTAG (IEEE 1149.1)<\/td>\n<\/tr>\n
Program\/Erase Cycles<\/td>\n20,000 minimum<\/td>\n<\/tr>\n
Data Retention<\/td>\n20 years<\/td>\n<\/tr>\n
Paquete<\/td>\nTSSOP-20<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to +70\u00b0C (C grade)<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • 4Mbit capacity sufficient for mid-size FPGA bitstreams<\/li>\n
  • 3.3V core supply with 1.8V to 3.3V I\/O compatibility<\/li>\n
  • Serial configuration interface with up to 33MHz clock rate<\/li>\n
  • JTAG in-system programming via IEEE 1149.1 boundary scan<\/li>\n
  • Cascadable for storing longer or multiple bitstreams<\/li>\n
  • Dedicated JTAG I\/O power supply (VCCJ) for flexible voltage interfacing<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Configuration storage for Xilinx Spartan-3 and Virtex-II FPGAs<\/li>\n
    • Embedded system FPGA bitstream storage<\/li>\n
    • Multi-FPGA daisy-chain configuration<\/li>\n
    • Prototype and production FPGA programming<\/li>\n
    • Legacy Xilinx FPGA design maintenance<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The XCF04SVOG20C from AMD\/Xilinx is a 4Mbit in-system programmable Platform Flash configuration PROM for Xilinx FPGAs. Supporting serial configuration modes at up to 33MHz with JTAG programming interface, it stores and loads FPGA bitstreams in a compact TSSOP-20 package. Key Specifications Density 4 Mbit (512 KB) Supply Voltage (VCCINT) 3.3V I\/O Voltage (VCCO) […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[19,13],"tags":[],"chip_brand":[175],"class_list":["post-7468","post","type-post","status-publish","format-standard","hentry","category-analog-linear-ics","category-integrated-circuits-ics","chip_brand-xilinx"],"acf":{"brief_explanation":"4Mbit FPGA config PROM, 3.3V, serial\/JTAG, 33MHz, TSSOP-20","date_code":"","package_case":"TSSOP-20 (6.5 x 4.4 mm)","in_stock":3890,"datasheet":"https:\/\/www.xilinx.com\/products\/intellectual-resource\/config-mem.html","price":".50 @ 1ku","product_introduction":"The XCF04SVOG20C is a member of the Xilinx Platform Flash PROM family, providing 4Mbit of in-system programmable non-volatile storage for Xilinx FPGA configuration bitstreams. Built on a low-power CMOS NOR Flash process, it supports Master Serial and Slave Serial configuration modes at clock rates up to 33MHz, with direct connection to the FPGA configuration pins (CCLK, DIN, PROGRAM_B, INIT_B, DONE). Programming is performed via the JTAG interface (IEEE 1149.1) using Xilinx iMPACT or Vivado tools. The dedicated VCCJ supply allows JTAG I\/O compatibility with voltage levels from 2.5V to 3.3V, while VCCO supports 1.8V to 3.3V for configuration interface compatibility with different FPGA voltage standards.","working_principle":"The XCF04SVOG20C operates through two primary modes. (1) In configuration mode, upon FPGA power-up, the FPGA asserts PROGRAM_B to clear its configuration memory, then releases it and signals readiness via INIT_B. The PROM detects the configuration start, asserts its internal address counter, and begins clocking data out on the D0 pin synchronized to CCLK from the FPGA. In Master Serial mode, the FPGA generates CCLK; in Slave Serial mode, an external clock drives both devices. (2) In JTAG programming mode, the TAP (Test Access Port) controller processes TCK, TMS, TDI, and TDO signals according to IEEE 1149.1, loading the Flash memory array with the FPGA bitstream. The JTAG interface also supports daisy-chaining multiple PROMs for larger bitstream storage and verification readback.","pin_description":"
      Pin<\/th>Name<\/th>Function<\/th><\/tr>
      1<\/td>TCK<\/td>JTAG test clock<\/td><\/tr>
      2<\/td>TDI<\/td>JTAG test data input<\/td><\/tr>
      3<\/td>TMS<\/td>JTAG test mode select<\/td><\/tr>
      4<\/td>TDO<\/td>JTAG test data output<\/td><\/tr>
      5<\/td>VCCJ<\/td>JTAG I\/O supply (2.5-3.3V)<\/td><\/tr>
      6<\/td>D0<\/td>Serial data output to FPGA DIN<\/td><\/tr>
      7<\/td>CF<\/td>Configuration flag\/control<\/td><\/tr>
      8<\/td>OE\/RESET<\/td>Output enable \/ reset<\/td><\/tr>
      9<\/td>CE<\/td>Chip enable<\/td><\/tr>
      10-20<\/td>Various<\/td>VCCINT, VCCO, GND, CLK, other control<\/td><\/tr><\/table>","application_scenarios":"
      • Configuration bitstream storage for Xilinx Spartan-3\/3E FPGAs in production designs<\/li>
      • Virtex-II FPGA configuration PROM for legacy system maintenance<\/li>
      • Multi-FPGA JTAG daisy-chain configuration systems<\/li>
      • Prototype development boards requiring in-system reprogrammable configuration<\/li>
      • Embedded control systems with Xilinx FPGA-based processing<\/li><\/ul>","alternative_models":"
        Model<\/th>Manufacturer<\/th>Key Difference<\/th><\/tr>
        XCF02SVOG20C<\/td>AMD\/Xilinx<\/td>2Mbit density, same package<\/td><\/tr>
        XCF01SVOG20C<\/td>AMD\/Xilinx<\/td>1Mbit density, same package<\/td><\/tr>
        XCF04SVOG20I<\/td>AMD\/Xilinx<\/td>Industrial temp -40\u00b0C to +85\u00b0C<\/td><\/tr>
        XCF08PVOG48C<\/td>AMD\/Xilinx<\/td>8Mbit, parallel config, VQ-48<\/td><\/tr>
        EPCQ16SI8N<\/td>Intel\/Altera<\/td>16Mbit, Altera FPGA config<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7468","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=7468"}],"version-history":[{"count":0,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/7468\/revisions"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=7468"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=7468"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=7468"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=7468"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}