The EPM570T144I5N from Intel (formerly Altera) is a MAX II CPLD with 570 logic elements in a TQFP-144 package. With instant-on configuration, 8Kbit UFM, and 5.3ns pin-to-pin delay, it provides flexible glue logic and protocol bridging.<\/p>\n
| Logic Elements<\/td>\n | 570<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||
| User I\/O<\/td>\n | 116 (TQFP-144 package)<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||
| UFM Storage<\/td>\n | 8,192 bits<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||
| tPD1 (pin-to-pin)<\/td>\n | 5.3 ns (fastest)<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||
| fCNT (global clock)<\/td>\n | 300 MHz<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||
| Core Voltage<\/td>\n | 1.8 V (with internal regulator)<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||
| I\/O Voltage<\/td>\n | 1.5 V \/ 1.8 V \/ 2.5 V \/ 3.3 V<\/td>\n<\/tr>\n | |||||||||||||||||||||||||||||||||||||||||
| Temperatura de funcionamiento<\/td>\n | -40C to +85C (I grade)<\/td>\n<\/tr>\n<\/table>\nCaracter\u00edsticas<\/h2>\nAplicaciones<\/h2>\nProduct Overview The EPM570T144I5N from Intel (formerly Altera) is a MAX II CPLD with 570 logic elements in a TQFP-144 package. With instant-on configuration, 8Kbit UFM, and 5.3ns pin-to-pin delay, it provides flexible glue logic and protocol bridging. Key Specifications Logic Elements 570 User I\/O 116 (TQFP-144 package) UFM Storage 8,192 bits tPD1 (pin-to-pin) 5.3 […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,49],"tags":[],"chip_brand":[196],"class_list":["post-7237","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-light-emitting-diodes-led","chip_brand-intel"],"acf":{"brief_explanation":"MAX II CPLD, 570 LE, TQFP-144, 116 I\/O, 8Kbit UFM, 5.3ns, instant-on, MultiVolt","date_code":"","package_case":"TQFP-144 (22.00 x 22.00 x 1.40 mm, 0.50mm pitch)","in_stock":9468,"datasheet":"https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/hb\/max2\/mx2_51002.pdf","price":"$8.00 @ 1ku","product_introduction":"The EPM570T144I5N from Intel (formerly Altera) is a MAX II CPLD with 570 logic elements in a TQFP-144 package. The MAX II architecture is based on a 2D row\/column structure of logic array blocks (LABs), each containing 10 logic elements (LEs). With 570 LEs, the EPM570 provides sufficient logic density for medium-complexity state machines, protocol bridging, and board-level glue logic that would otherwise require multiple discrete ICs. A key advantage of the MAX II family is instant-on configuration: the device configures from its built-in Flash memory in under 300us after power-up, eliminating the external configuration device required by FPGAs and providing deterministic startup behavior. The 8Kbit User Flash Memory (UFM) block provides non-volatile on-chip storage for calibration coefficients, version IDs, and other parameters, reducing external EEPROM requirements. The MultiVolt I\/O feature allows the device to interface with components at 1.5V, 1.8V, 2.5V, or 3.3V I\/O voltages, with separate VCCIO banks. The internal voltage regulator accepts 3.3V I\/O supply and generates the 1.8V core voltage, simplifying the power supply design.","working_principle":"The EPM570T144I5N uses the MAX II CPLD architecture based on Flash-configured logic. (1) Logic Array: The device contains 57 LABs, each with 10 LEs. Each LE consists of a 4-input look-up table (LUT), a programmable register, and carry\/interconnect logic. The LUT can implement any 4-input Boolean function, and the register provides sequential logic capability. (2) Interconnect: The MultiTrack interconnect structure provides high-speed routing between LEs, LABs, and I\/O elements. Dedicated clock networks distribute low-skew clock signals across the device. (3) Configuration: At power-up, the internal Flash memory automatically configures the SRAM configuration cells in under 300us. The device is immediately ready for operation, unlike FPGAs that require external configuration loading. (4) UFM: The 8Kbit User Flash Memory is a separate Flash sector that can be read and written by the logic array during operation, providing non-volatile storage independent of the configuration data. (5) JTAG: The JTAG interface provides in-system programming of the Flash memory and boundary-scan testing.","pin_description":"
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