{"id":6764,"date":"2026-06-21T10:28:12","date_gmt":"2026-06-21T10:28:12","guid":{"rendered":"https:\/\/materialparts.com\/epm3128atc100-10\/"},"modified":"2026-06-21T10:28:12","modified_gmt":"2026-06-21T10:28:12","slug":"epm3128atc100-10","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/epm3128atc100-10\/","title":{"rendered":"EPM3128ATC100-10"},"content":{"rendered":"

Productos<\/h2>\n

The EPM3128ATC100-10 from Intel (formerly Altera) is a MAX 3000A CPLD with 128 macrocells, 2500 usable gates, 80 I\/O pins, 10 ns propagation delay, and in-system programmability in a 100-pin TQFP package.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Family<\/td>\nMAX 3000A<\/td>\n<\/tr>\n
Macrocells<\/td>\n128<\/td>\n<\/tr>\n
Usable Gates<\/td>\n2500<\/td>\n<\/tr>\n
Logic Array Blocks<\/td>\n8<\/td>\n<\/tr>\n
I\/O Pins<\/td>\n80<\/td>\n<\/tr>\n
Propagation Delay (TPD)<\/td>\n10 ns (max)<\/td>\n<\/tr>\n
Counter Frequency<\/td>\nUp to 192.3 MHz<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n3.0 V to 3.6 V (3.3V nominal)<\/td>\n<\/tr>\n
Programming<\/td>\nIn-System Programmable (ISP) via JTAG<\/td>\n<\/tr>\n
Paquete<\/td>\nTQFP-100 (14 x 14 mm)<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n0\u00b0C to 70\u00b0C<\/td>\n<\/tr>\n
Product Status<\/td>\nObsolete<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • 128 macrocells with programmable logic and I\/O<\/li>\n
  • In-system programmable via JTAG IEEE 1149.1<\/li>\n
  • 10 ns pin-to-pin propagation delay<\/li>\n
  • Supports 2.5V, 3.3V, and 5V I\/O standards<\/li>\n
  • EEPROM-based configuration (non-volatile)<\/li>\n
  • Boundary-scan test capability<\/li>\n
  • Multiple low-power modes<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Glue logic and address decoding<\/li>\n
    • Bus bridging and protocol conversion<\/li>\n
    • I\/O expansion and interface adaptation<\/li>\n
    • Control industrial y automatizaci\u00f3n<\/li>\n
    • Legacy system replacement and migration<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The EPM3128ATC100-10 from Intel (formerly Altera) is a MAX 3000A CPLD with 128 macrocells, 2500 usable gates, 80 I\/O pins, 10 ns propagation delay, and in-system programmability in a 100-pin TQFP package. Key Specifications Family MAX 3000A Macrocells 128 Usable Gates 2500 Logic Array Blocks 8 I\/O Pins 80 Propagation Delay (TPD) 10 […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[196],"class_list":["post-6764","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-intel"],"acf":{"brief_explanation":"MAX 3000A CPLD, 128 MC, 2500 Gates, 80 I\/O, 10ns TPD, 3.3V, TQFP-100","date_code":"","package_case":"TQFP-100 (14 x 14 x 1.2 mm, 0.5mm pitch)","in_stock":486,"datasheet":"https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/ds\/m3000a.pdf","price":"$19.27 @ 1u","product_introduction":"The EPM3128ATC100-10 from Intel (formerly Altera) is a member of the MAX 3000A family of high-performance, EEPROM-based complex programmable logic devices (CPLDs). With 128 macrocells organized into 8 logic array blocks and 2500 usable gates, it provides flexible logic implementation for medium-complexity designs. The device features 10 ns maximum pin-to-pin propagation delay and supports counter frequencies up to 192.3 MHz. In-system programming (ISP) through the JTAG interface allows firmware updates without removing the device from the board. The EEPROM-based configuration provides instant-on operation with no external configuration device required. The device is now obsolete and recommended for replacement with newer CPLD or low-end FPGA families.","working_principle":"The EPM3128ATC100-10 uses the MAX 3000A architecture based on logic array blocks (LABs) interconnected by a programmable interconnect array (PIA). Each LAB contains 16 macrocells, and the device has 8 LABs for a total of 128 macrocells. Each macrocell consists of a programmable AND\/OR array, a configurable register (D, T, JK, or SR flip-flop), and programmable I\/O cell. The PIA routes signals between LABs and from I\/O pins. Configuration data is stored in EEPROM cells, making the device non-volatile and instantly operational at power-up. JTAG interface provides in-system programming and boundary-scan test capability. The device supports mixed-voltage operation with 3.3V core and compatibility with 2.5V, 3.3V, and 5V I\/O standards through input tolerance.","pin_description":"
      Pin Group<\/th>Name<\/th>Type<\/th>Function<\/th><\/tr>
      Multiple<\/td>IO0-IO79<\/td>I\/O<\/td>80 user I\/O pins (3.3V)<\/td><\/tr>
      4 pins<\/td>VCCINT<\/td>Power<\/td>3.3V internal core supply<\/td><\/tr>
      4 pins<\/td>GNDINT<\/td>Ground<\/td>Internal core ground<\/td><\/tr>
      4 pins<\/td>VCCIO<\/td>Power<\/td>I\/O supply (3.3V)<\/td><\/tr>
      4 pins<\/td>GNDIO<\/td>Ground<\/td>I\/O ground<\/td><\/tr>
      1 pin<\/td>TDI<\/td>Input<\/td>JTAG test data input<\/td><\/tr>
      1 pin<\/td>TDO<\/td>Output<\/td>JTAG test data output<\/td><\/tr>
      1 pin<\/td>TMS<\/td>Input<\/td>JTAG test mode select<\/td><\/tr>
      1 pin<\/td>TCK<\/td>Input<\/td>JTAG test clock<\/td><\/tr><\/table>","application_scenarios":"
      • Address decoding and memory interface glue logic<\/li>
      • PCI and bus bridge logic conversion<\/li>
      • Legacy ASIC replacement in mature systems<\/li>
      • Industrial PLC I\/O expansion modules<\/li>
      • Communication protocol bridging (SPI to parallel)<\/li><\/ul>","alternative_models":"
        Manufacturer<\/th>Part Number<\/th>Package<\/th>Notes<\/th><\/tr>
        Intel<\/td>EPM3128ATC100-10N<\/td>TQFP-100<\/td>Lead-free version<\/td><\/tr>
        Intel<\/td>EPM570T100I5N<\/td>TQFP-100<\/td>MAX II, 440 MC, 3.3V<\/td><\/tr>
        Lattice<\/td>LC4032V-10TN100I<\/td>TQFP-100<\/td>ispMACH 4000V, 32 MC<\/td><\/tr>
        Xilinx<\/td>XC2C128-7VQ100I<\/td>VQFP-100<\/td>CoolRunner-II, 128 MC<\/td><\/tr>
        Intel<\/td>10M04SCE144I7G<\/td>EQFP-144<\/td>MAX 10 FPGA, 4K LEs<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/6764","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=6764"}],"version-history":[{"count":0,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/6764\/revisions"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=6764"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=6764"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=6764"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=6764"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}