{"id":6460,"date":"2026-06-16T03:57:22","date_gmt":"2026-06-16T03:57:22","guid":{"rendered":"https:\/\/materialparts.com\/sn74lvc1g86dckr\/"},"modified":"2026-06-16T03:57:22","modified_gmt":"2026-06-16T03:57:22","slug":"sn74lvc1g86dckr","status":"publish","type":"post","link":"https:\/\/materialparts.com\/es\/sn74lvc1g86dckr\/","title":{"rendered":"SN74LVC1G86DCKR"},"content":{"rendered":"

Productos<\/h2>\n

The SN74LVC1G86DCKR is a single 2-input exclusive-OR (XOR) gate from Texas Instruments for 1.65V to 5.5V operation. It performs Y = A\u2295B in positive logic: output is high when inputs differ. If one input is low, the other passes through in true form; if one input is high, the other is inverted. This versatile function enables parity generation, controlled inversion, and comparison logic. Features 4ns max tpd, \u00b124mA drive, 5.5V OVT inputs, and Ioff.<\/p>\n

Especificaciones<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Logic Function<\/td>\nXOR (Y = A\u2295B = \u0100B + AB\u0304)<\/td>\n<\/tr>\n
Tensi\u00f3n de alimentaci\u00f3n<\/td>\n1.65V to 5.5V<\/td>\n<\/tr>\n
Propagation Delay (tpd)<\/td>\n4ns max @ 3.3V, 15pF load<\/td>\n<\/tr>\n
Output Drive<\/td>\n\u00b124mA @ 3.3V; \u00b132mA @ 4.5V<\/td>\n<\/tr>\n
Quiescent Current (ICC)<\/td>\n10\u00b5A max<\/td>\n<\/tr>\n
Input Voltage Tolerance<\/td>\nUp to 5.5V (overvoltage tolerant)<\/td>\n<\/tr>\n
Down Translation<\/td>\nYes<\/td>\n<\/tr>\n
Ioff Support<\/td>\nYes<\/td>\n<\/tr>\n
ESD Protection<\/td>\n2000V HBM, 1000V CDM<\/td>\n<\/tr>\n
Latch-Up<\/td>\n>100mA per JESD 78 Class II<\/td>\n<\/tr>\n
Paquete<\/td>\nSC70-5 \/ SOT-353 (2.0 x 1.25mm)<\/td>\n<\/tr>\n
Temperatura de funcionamiento<\/td>\n-40\u00b0C to +125\u00b0C<\/td>\n<\/tr>\n<\/table>\n

Caracter\u00edsticas<\/h2>\n
    \n
  • Exclusive-OR function: Y = A\u2295B<\/li>\n
  • 1.65V to 5.5V VCC operation<\/li>\n
  • 5.5V overvoltage-tolerant inputs<\/li>\n
  • 4ns max propagation delay at 3.3V<\/li>\n
  • 10\u00b5A max quiescent current<\/li>\n
  • \u00b124mA output drive at 3.3V<\/li>\n
  • Controlled inversion: one input selects true\/invert<\/li>\n
  • Ioff for partial-power-down support<\/li>\n
  • Five equivalent XOR symbol representations<\/li>\n
  • NanoFree package available<\/li>\n<\/ul>\n

    Aplicaciones<\/h2>\n
      \n
    • Controlled signal inversion (true\/complement)<\/li>\n
    • Parity generation and checking<\/li>\n
    • Phase detection and comparison<\/li>\n
    • Data scrambling\/descrambling<\/li>\n
    • Edge detection (change detection)<\/li>\n
    • BPSK modulation control<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LVC1G86DCKR is a single 2-input exclusive-OR (XOR) gate from Texas Instruments for 1.65V to 5.5V operation. It performs Y = A\u2295B in positive logic: output is high when inputs differ. If one input is low, the other passes through in true form; if one input is high, the other is inverted. This […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[],"chip_brand":[138],"class_list":["post-6460","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","chip_brand-ti"],"acf":{"brief_explanation":"Single 2-input XOR gate, 1.65-5.5V, 4ns tpd, \u00b124mA, OVT inputs, controlled inversion, SC70-5","date_code":"","package_case":"SC70-5 \/ SOT-353 (2.0 x 1.25 x 1.0mm)","in_stock":48000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74lvc1g86.pdf","price":"$0.030 @ 1ku","product_introduction":"The SN74LVC1G86DCKR is a single 2-input exclusive-OR (XOR) gate from Texas Instruments' LVC family, designed for 1.65V to 5.5V VCC operation. It performs Y = A\u2295B (equivalently Y = \u0100B + AB\u0304) in positive logic. The XOR function outputs high when the two inputs are different. A key property: if one input is held low, the other input passes through in true form (buffering); if one input is held high, the other input appears inverted at the output. This 'controlled inversion' makes the XOR gate invaluable for BPSK modulation, data scrambling, and selectable true\/complement signal routing. The device supports 5.5V overvoltage-tolerant inputs, down-translation, and Ioff partial-power-down isolation.","working_principle":"The SN74LVC1G86 implements the XOR function using a CMOS transmission-gate-based design. When input A is low, transmission gates route input B directly to the output (true form). When input A is high, transmission gates route input B inverted to the output. This implementation is more compact and faster than the classic AND-OR-INVERT approach. The truth table is: A=0,B=0\u2192Y=0; A=0,B=1\u2192Y=1; A=1,B=0\u2192Y=1; A=1,B=1\u2192Y=0. The output is high exactly when inputs differ. Overvoltage-tolerant inputs use isolation transistors, and the Ioff circuit disconnects the output when VCC is removed for safe partial-power-down operation.","pin_description":"
      Pin<\/th>Name<\/th>Description<\/th><\/tr>
      1<\/td>1A<\/td>Input A<\/td><\/tr>
      2<\/td>1B<\/td>Input B<\/td><\/tr>
      3<\/td>GND<\/td>Ground<\/td><\/tr>
      4<\/td>Y<\/td>Output (Y = A\u2295B)<\/td><\/tr>
      5<\/td>VCC<\/td>Supply voltage (1.65V to 5.5V)<\/td><\/tr><\/table>","application_scenarios":"
      • Controlled Inverter (BPSK):<\/b> Connect a data signal to input A and a modulation\/control signal to input B. When B=0, Y=A (data passes through). When B=1, Y=\u0100 (data is inverted). This is the basis of binary phase-shift keying (BPSK) modulation and data scrambling. A single XOR gate implements the complete function.<\/li>
      • Parity Generator:<\/b> Cascade XOR gates to compute the parity of a multi-bit data word. For 8-bit parity, XOR bits 0-1, then XOR the result with bit 2, and so on. The final output is the parity bit. The 4ns propagation delay supports high-speed parity computation in communication protocols.<\/li>
      • Edge\/Change Detector:<\/b> Connect a signal to input A and a delayed version of the same signal (via RC or buffer delay) to input B. The XOR output pulses high during the transition when A and B differ, detecting edges (both rising and falling). The pulse width equals the delay, adjustable by the RC time constant.<\/li><\/ul>","alternative_models":"
        Model<\/th>Function<\/th>Key Difference<\/th><\/tr>
        SN74LVC1G86DBVR<\/td>XOR gate<\/td>SOT-23-5, larger package<\/td><\/tr>
        SN74LVC2G86DCTR<\/td>Dual XOR<\/td>2 channels, VSSOP-8<\/td><\/tr>
        74AUP1G86GF<\/td>XOR gate<\/td>Nexperia, 0.8V min, ultra-low power<\/td><\/tr>
        NC7SZ86P5X<\/td>XOR gate<\/td>Renesas\/IDT, similar specs<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/6460","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/comments?post=6460"}],"version-history":[{"count":0,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/posts\/6460\/revisions"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/media?parent=6460"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/categories?post=6460"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/tags?post=6460"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/es\/wp-json\/wp\/v2\/chip_brand?post=6460"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}