El TLA2024IRUGT de Texas Instruments es un ADC delta-sigma de 12 bits y 4 canales con interfaz I2C en un encapsulado X2QFN de 10 patillas (2,0 x 1,5 mm). Dispone de un multiplexor de entrada flexible (4 de un solo extremo o 2 diferenciales), amplificador de ganancia programable (1x\/2x\/4x\/8x a x16), referencia de tensi\u00f3n interna, oscilador interno, velocidad de datos de 128 SPS a 3,3 kSPS, corriente de alimentaci\u00f3n de 150 uA, rango de alimentaci\u00f3n de 2V a 5,5V y 3 direcciones I2C seleccionables mediante patillas. Conversi\u00f3n continua o de disparo \u00fanico. Consumo t\u00edpico de 0,9 mW. Temperatura de funcionamiento de -40C a +85C. Embalaje en cinta y carrete.<\/p>","protected":false},"excerpt":{"rendered":"
The TLA2024IRUGT from Texas Instruments is a 12-bit 4-channel delta-sigma ADC with I2C interface in a 10-pin X2QFN package (2.0 x 1.5 mm). It features a flexible input multiplexer (4 single-ended or 2 differential), programmable gain amplifier (1x\/2x\/4x\/8x to x16), internal voltage reference, internal oscillator, 128 SPS to 3.3 kSPS data rate, 150 uA supply […]<\/p>\n","protected":false},"author":2,"featured_media":2248,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-2084","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"12-bit 4ch delta-sigma ADC, PGA x1-16, I2C, int ref, X2QFN 2x1.5mm, T\/R","date_code":"","package_case":"10-X2QFN (2.05 x 1.55 x 0.35 mm, 0.5mm pitch, leadless)","in_stock":1380,"datasheet":"https:\/\/www.ti.com\/product\/TLA2024","price":"$1.06 (250+ pcs)","product_introduction":"The TLA2024IRUGT from Texas Instruments is an ultra-small, cost-optimized 12-bit delta-sigma ADC with 4-channel input multiplexer and programmable gain amplifier in a 10-pin X2QFN package measuring just 2.0 x 1.5 mm. It is the highest-channel-density variant of the TLA202x family, offering 4 single-ended or 2 differential input channels at only 0.75 mm2 per channel.\n\nThe TLA2024 features a flexible input multiplexer that can be configured as four single-ended inputs (AIN0-GND, AIN1-GND, AIN2-GND, AIN3-GND) or two differential input pairs (AIN0-AIN1, AIN2-AIN3). The multiplexer is software-configurable via the I2C interface, allowing sequential scanning of multiple input channels.\n\nThe integrated programmable gain amplifier (PGA) provides gain settings of x1, x2, x4, x8, and x16 (note: some sources list up to x16 while others list x8 maximum). At maximum PGA gain, the input range is reduced to +\/-256 mV (at x8) or +\/-128 mV (at x16), enabling direct measurement of small signals from current sense resistors, thermocouples, and bridge sensors without external amplification. The PGA has input ranges from +\/-6.144V (x1) down to +\/-256 mV (x8).\n\nThe device integrates a voltage reference, oscillator, and I2C interface. The internal 2.048V reference provides the ADC full-scale reference. The I2C interface supports standard mode and fast mode, with three pin-selectable addresses.\n\nThe TLA2024 provides 12-bit resolution with programmable data rates from 128 SPS to 3.3 kSPS. The delta-sigma architecture provides inherent anti-aliasing and good noise performance. INL is 1 LSB typical, and full-scale error is 0.05% FSR typical. No missing codes are guaranteed to 12 bits.\n\nThe 0.9 mW typical power consumption and single-shot conversion mode make the TLA2024 suitable for power-constrained applications. In single-shot mode, the device automatically powers down after each conversion, reducing average current to microamps at low sampling rates.\n\nThe X2QFN package has a land pattern of only 3 mm2, making it the industry's smallest 4-channel 12-bit ADC. This enables placement directly at sensor nodes in space-constrained systems.\n\nThe TLA2024 shares the same datasheet (SBAS975) with the TLA2021 and TLA2022. The key differences are: TLA2021 = 1-channel, no PGA; TLA2022 = 1-channel with PGA; TLA2024 = 4-channel with PGA and MUX.","working_principle":"**Delta-Sigma ADC with PGA and MUX:** The input signal first passes through the analog multiplexer, which selects one of four single-ended or two differential input configurations. The selected signal is then amplified by the PGA, digitized by the delta-sigma modulator, and filtered by the SINC digital decimation filter to produce a 12-bit output word.\n\n**Input Multiplexer:** The 4:1 (single-ended) or 2:1 (differential) multiplexer is controlled by the MUX[2:0] bits in the configuration register. Channel switching requires a settling time before the conversion result is valid, typically one conversion cycle.\n\n**PGA Operation:** The PGA amplifies the input signal before the modulator. At x1 gain, the full-scale input range is +\/-6.144V (well beyond VDD, but limited by absolute maximum ratings to VDD+0.3V). At x2: +\/-4.096V. At x4: +\/-2.048V. At x8: +\/-1.024V (some sources: +\/-256mV). Higher gain reduces the input range but improves the effective resolution for small signals. The PGA input common-mode range must be within GND-0.1V to VDD+0.1V.\n\n**Conversion and Data Format:** The 12-bit conversion result is output in 16-bit two's complement format, left-justified. At PGA = x1, 1 LSB = 187.5 uV (6.144V \/ 32768). At PGA = x8, 1 LSB = 23.4 uV (1.024V \/ 32768, if 12-bit effective).\n\n**I2C Protocol:** Write to the 16-bit configuration register to set MUX, PGA, mode, and data rate. Read 2 bytes (16 bits) for conversion result. The OS bit starts a single-shot conversion when written as 1. The ALERT\/RDY pin can signal conversion completion or out-of-range conditions.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| A1<\/td> | AIN0<\/td> | I<\/td> | Analog input 0; positive input for differential pair 0; single-ended input 0; 0 to VDD range; MUX selectable<\/td><\/tr> | ||||||||||||||||||||||||
| A2<\/td> | AIN1<\/td> | I<\/td> | Analog input 1; negative input for differential pair 0; single-ended input 1; 0 to VDD range; MUX selectable<\/td><\/tr> | ||||||||||||||||||||||||
| B1<\/td> | GND<\/td> | G<\/td> | Ground; connect to PCB ground plane<\/td><\/tr> | ||||||||||||||||||||||||
| B2<\/td> | ADDR<\/td> | I<\/td> | I2C address select; GND = 0x48; VDD = 0x49; SDA = 0x4A; must be tied to defined state<\/td><\/tr> | ||||||||||||||||||||||||
| C1<\/td> | SDA<\/td> | I\/O<\/td> | I2C data; open-drain; requires external pull-up (4.7kOhm typical); fast-mode compatible<\/td><\/tr> | ||||||||||||||||||||||||
| C2<\/td> | SCL<\/td> | I<\/td> | I2C clock; requires external pull-up (4.7kOhm typical); up to 400kHz<\/td><\/tr> | ||||||||||||||||||||||||
| D1<\/td> | ALERT\/RDY<\/td> | O<\/td> | Alert\/Ready output; active-low open-drain; conversion complete or comparator threshold exceeded; connect pull-up if used<\/td><\/tr> | ||||||||||||||||||||||||
| D2<\/td> | VDD<\/td> | P<\/td> | Supply voltage; 2V to 5.5V; decouple with 0.1uF ceramic to GND<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
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