El TPS51362RVER de Texas Instruments es un convertidor reductor s\u00edncrono de 10 A y entrada de 3 V a 22 V con MOSFET integrados en un encapsulado VQFN-CLIP de 28 patillas (4,5\u00d73,5 mm, paso de 0,4 mm). Utiliza la topolog\u00eda de control D-CAP2 de TI para un funcionamiento sin compensaci\u00f3n con condensadores de salida POSCAP o totalmente MLCC, una frecuencia de conmutaci\u00f3n fija de 800 kHz y un modo ULQ que consume s\u00f3lo 100 \u00b5A en modo de espera de bajo consumo. La tensi\u00f3n de salida es programable de 0,6 V a 2,0 V mediante pin-strapping (1,05\/1,2\/1,35\/1,5 V fijos) o divisor de resistencias. Entre sus caracter\u00edsticas se incluyen el arranque suave programable, el buen estado de la alimentaci\u00f3n, la descarga de salida y la protecci\u00f3n OCL\/OVP\/UVP\/UVLO\/apagado t\u00e9rmico. Dirigido a carriles DDR VDDQ\/VCCIO y convertidores POL en port\u00e1tiles y sistemas integrados.<\/p>","protected":false},"excerpt":{"rendered":"
The TPS51362RVER from Texas Instruments is a 3-V to 22-V input, 10-A synchronous step-down converter with integrated MOSFETs in a 28-pin VQFN-CLIP package (4.5\u00d73.5 mm, 0.4-mm pitch). It uses TI’s D-CAP2 control topology for compensation-less operation with POSCAP or all-MLCC output capacitors, fixed 800-kHz switching frequency, and ULQ mode drawing only 100 \u00b5A in low-power […]<\/p>\n","protected":false},"author":2,"featured_media":2871,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[31,13],"tags":[],"chip_brand":[138],"class_list":["post-2035","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-dc-dc-converters","category-integrated-circuits-ics","chip_brand-ti"],"acf":{"brief_explanation":"22V 10A sync buck, D-CAP2, 800kHz, 100\u00b5A ULQ standby, 0.6-2.0Vout, VQFN-CLIP 28-pin 4.5x3.5mm, -10~85\u00b0C","date_code":"","package_case":"VQFN-CLIP-28 (RVE) (4.5 x 3.5 x 1.0 mm, 0.4mm pitch)","in_stock":1200,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/tps51362.pdf","price":"$2.29 (1K+ pcs)","product_introduction":"The TPS51362RVER is a 10-A integrated-FET synchronous buck converter from Texas Instruments, designed for point-of-load (POL) applications in notebook computers and embedded systems. It operates from a 3-V to 22-V input and produces an adjustable output from 0.6 V to 2.0 V, covering DDR memory VDDQ (1.35 V), VCCIO (1.05 V, 1.2 V), and core logic rails.\n\nThe D-CAP2 control topology is the key differentiator. Unlike traditional current-mode or voltage-mode control, D-CAP2 uses adaptive on-time control with internal ripple injection, eliminating the need for Type-II\/III compensation components. This simplifies design and supports both POSCAP and all-MLCC output capacitor configurations without stability concerns \u2014 a critical advantage in compact designs where MLCCs are preferred for height and reliability.\n\nThe ULQ (Ultra-Low Quiescent) mode reduces the bias current to 100 \u00b5A when the LP# pin is pulled low, enabling long battery life during system standby. This is a significant improvement over standard auto-skip modes that typically draw 500 \u00b5A to 1 mA. In normal PWM mode, the device operates at a fixed 800-kHz frequency, balancing efficiency and inductor size.\n\nThe output voltage can be set by pin-strapping REFIN and REFIN2 pins (1.05 V, 1.2 V, 1.35 V, 1.5 V fixed options) without external resistors, or by a resistor divider from the 2.0-V VREF pin for any voltage from 0.6 V to 2.0 V. This flexibility supports multiple DDR generations and rail voltages with a single BOM.\n\nThe integrated bootstrap MOSFET switch eliminates the need for an external bootstrap diode. The low-side MOSFET RDS(on) sensing provides temperature-compensated overcurrent protection without an external sense resistor. The VQFN-CLIP-28 package achieves a compact 15.75-mm\u00b2 footprint with an exposed thermal pad for efficient heat dissipation.","working_principle":"**D-CAP2 Control:** The TPS51362 uses TI's D-CAP2 (Direct Capacitor-Area-Free 2nd generation) control, which combines adaptive on-time modulation with internal ripple injection. The error amplifier compares FB against an internal reference; the on-time generator produces a fixed-duration pulse (proportional to VIN\/VOUT) each switching cycle. Internal ripple injection at FB emulates the inductor current ripple, providing the information needed for stable operation without external compensation. This topology is inherently stable with any output capacitor type (POSCAP, MLCC, or mixed) as long as ESR is above a minimum threshold.\n\n**ULQ Mode:** When LP# is pulled low, the device enters ultra-low-quiescent mode. The controller reduces internal bias currents and switches to a pulse-skip mode where the switching frequency scales with load. At zero load, only 100 \u00b5A is drawn from the input supply. The output voltage regulation accuracy degrades slightly in ULQ mode but remains within DDR specification limits.\n\n**Power Stage:** The integrated high-side and low-side MOSFETs are optimized for low duty-cycle operation (3-5 V output from 12-19 V input). The low-side RDS(on) is also used for current sensing \u2014 the voltage across the low-side FET during the off-time is measured and temperature-compensated to set the overcurrent limit threshold, eliminating an external sense resistor.\n\n**Bootstrap and Pre-Bias:** The integrated bootstrap switch charges the BOOT capacitor from VDD through an internal MOSFET (not a diode), reducing the BOOT voltage drop and enabling start-up into pre-biased outputs without discharging the load first.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | VDD<\/td> | P<\/td> | Internal 5V LDO output and internal supply bypass; connect 1\u00b5F ceramic to GND; do not load externally<\/td><\/tr> | ||||||||||||||||||||||||||||
| 2<\/td> | EN<\/td> | I<\/td> | Enable; pull high to enable; has internal pull-up; pull below 0.4V to disable; UVLO threshold ~4.5V on VIN<\/td><\/tr> | ||||||||||||||||||||||||||||
| 3<\/td> | LP#<\/td> | I<\/td> | Low-power mode control; pull low for ULQ mode (100\u00b5A Iq); pull high for normal PWM\/auto-skip; has internal pull-up<\/td><\/tr> | ||||||||||||||||||||||||||||
| 4<\/td> | PGOOD<\/td> | O<\/td> | Open-drain power-good output; asserts when FB is within \u00b110% of target; connect external pull-up resistor to logic supply<\/td><\/tr> | ||||||||||||||||||||||||||||
| 5<\/td> | VFB<\/td> | I<\/td> | Voltage feedback input; connect to output voltage divider midpoint or tie to VREF for resistor-less fixed voltage; reference 0.6V<\/td><\/tr> | ||||||||||||||||||||||||||||
| 6<\/td> | VREF<\/td> | O<\/td> | 2.0V reference output; 300\u00b5A source capability; bypass with 0.1\u00b5F to GND; use for resistor-divider output voltage setting<\/td><\/tr> | ||||||||||||||||||||||||||||
| 7<\/td> | REFIN<\/td> | I<\/td> | Output voltage select pin 1; float or tie to GND during startup to select fixed voltage (see truth table); determines 1.05\/1.2\/1.5\/1.35V<\/td><\/tr> | ||||||||||||||||||||||||||||
| 8<\/td> | REFIN2<\/td> | I<\/td> | Output voltage select pin 2; same function as REFIN; both pins sampled at startup; latched until next power cycle<\/td><\/tr> | ||||||||||||||||||||||||||||
| 9<\/td> | SS<\/td> | I\/O<\/td> | Soft-start programming; connect capacitor to GND; 5\u00b5A charge current; larger cap = slower start; leave floating for default 1ms<\/td><\/tr> | ||||||||||||||||||||||||||||
| 10<\/td> | MODE<\/td> | I<\/td> | Operation mode select; controls auto-skip vs forced-PWM behavior; tie to GND or float per datasheet recommendation<\/td><\/tr> | ||||||||||||||||||||||||||||
| 11-18<\/td> | GND<\/td> | G<\/td> | Signal and power ground; connect to PCB ground plane and exposed thermal pad; critical for thermal and electrical performance<\/td><\/tr> | ||||||||||||||||||||||||||||
| 19<\/td> | SW<\/td> | O<\/td> | Switch node; connect to output inductor; high dv\/dt; keep copper short to reduce EMI; abs max -1.5V to 24V<\/td><\/tr> | ||||||||||||||||||||||||||||
| 20<\/td> | BOOT<\/td> | I\/O<\/td> | Bootstrap capacitor; connect 0.1\u00b5F ceramic from BOOT to SW; internal bootstrap switch charges from VDD<\/td><\/tr> | ||||||||||||||||||||||||||||
| 21<\/td> | VIN<\/td> | P<\/td> | Main input supply (3-22V); connect input bypass capacitors (10\u00b5F ceramic + bulk) close to pin; high-frequency decoupling critical<\/td><\/tr> | ||||||||||||||||||||||||||||
| 22-28<\/td> | VIN\/GND<\/td> | P\/G<\/td> | Additional VIN and GND pins for power distribution and thermal relief; follow PCB layout guidelines per datasheet<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|