El ADG1434YRUZ-REEL7 de Analog Devices es un conmutador anal\u00f3gico iCMOS SPDT (unipolar, doble tiro) cu\u00e1druple con una resistencia de activaci\u00f3n t\u00edpica de 4 ohmios en un encapsulado TSSOP de 20 terminales con embalaje de cinta y carrete (carrete de 7 pulgadas). Especificaciones principales con alimentaci\u00f3n doble de m\u00e1s o menos 15 V: resistencia de activaci\u00f3n t\u00edpica de 4 ohmios (4,7 ohmios como m\u00e1ximo a 25 \u00baC, 5,7 ohmios como m\u00e1ximo a 85 \u00baC, 6,7 ohmios como m\u00e1ximo a 125 \u00baC); coincidencia de resistencia de activaci\u00f3n entre canales t\u00edpica de 0,55 ohmios; planitud de resistencia de activaci\u00f3n t\u00edpica de 0,5 ohmios; rango de se\u00f1al anal\u00f3gica de VSS a VDD (de carril a carril); corriente continua por canal de hasta 115 mA; fuga de desactivaci\u00f3n de fuente t\u00edpica de 0,02 nA (3 nA como m\u00e1ximo a 85 \u00baC); fuga de desactivaci\u00f3n de drenaje t\u00edpica de 0,02 nA; fuga de activaci\u00f3n de canal t\u00edpica de 0,02 nA.02 nA t\u00edpica; fuga de canal encendido 0,04 nA t\u00edpica; tiempo de transici\u00f3n 315 ns t\u00edpica a m\u00e1s o menos 5 V (170 ns a m\u00e1s o menos 15 V); retardo de tiempo de ruptura antes de la realizaci\u00f3n 90 ns m\u00ednimo; tiempo de encendido 325 ns t\u00edpica a m\u00e1s o menos 5 V; tiempo de apagado 150 ns t\u00edpica a m\u00e1s o menos 5 V; inyecci\u00f3n de carga -10 pC t\u00edpica a m\u00e1s o menos 5 V; aislamiento apagado -70 dB t\u00edpica a 1 MHz; diafon\u00eda de canal a canal -70 dB t\u00edpica a 1 MHz; THD m\u00e1s N 0.06 por ciento t\u00edpica de 20 Hz a 20 kHz; ancho de banda de -3 dB 145 MHz t\u00edpica a m\u00e1s o menos 5 V (200 MHz a m\u00e1s o menos 15 V); entradas digitales compatibles con l\u00f3gica de 3 V (VIH = 2,0 V, VIL = 0,8 V); corriente de alimentaci\u00f3n IDD = 18 uA t\u00edpica, ISS = 0.5 uA t\u00edpica; preparado para m\u00e1s o menos 15 V, m\u00e1s 12 V simple, o m\u00e1s o menos 5 V doble alimentaci\u00f3n; temperatura de funcionamiento -40 a +125 grados C (versi\u00f3n Y); entrada EN en versi\u00f3n LFCSP (no en TSSOP); acci\u00f3n de conmutaci\u00f3n break-before-make; proceso iCMOS; cumple RoHS. Estado de la producci\u00f3n.<\/p>","protected":false},"excerpt":{"rendered":"
The ADG1434YRUZ-REEL7 from Analog Devices is a quad SPDT (single-pole, double-throw) iCMOS analog switch with 4 Ohm typical on-resistance in a 20-lead TSSOP package with tape and reel packaging (7-inch reel). Key specifications at plus or minus 15 V dual supply: on-resistance 4 Ohm typical (4.7 Ohm maximum at 25 degrees C, 5.7 Ohm maximum […]<\/p>\n","protected":false},"author":2,"featured_media":2892,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13],"tags":[],"chip_brand":[165],"class_list":["post-1994","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-integrated-circuits-ics","chip_brand-adi"],"acf":{"brief_explanation":"Quad SPDT analog switch, 4Ohm Ron, +\/-15V\/+12V\/+\/-5V, 115mA\/ch, BBM, -70dB off-isolation, 200MHz BW, TSSOP-20, -40~125C","date_code":"","package_case":"TSSOP-20 (RU-20) (6.5 x 4.4 x 1.05 mm, 0.65mm pitch)","in_stock":3000,"datasheet":"https:\/\/www.analog.com\/en\/products\/adg1434.html","price":"$4.25 (1K+ pcs)","product_introduction":"The ADG1434YRUZ-REEL7 from Analog Devices is a quad SPDT (4-channel, 2:1 multiplexer) analog switch built on the iCMOS (industrial CMOS) process, offering very low on-resistance (4 Ohm typical) with excellent on-resistance flatness (0.5 Ohm) and channel matching (0.55 Ohm), making it ideal for precision signal routing applications where distortion and signal integrity are critical.\n\nThe iCMOS process is Analog Devices' proprietary technology that combines high-voltage CMOS with bipolar transistors, enabling analog switches that can operate at high supply voltages (up to plus or minus 16.5 V or 33 V single supply) while achieving low on-resistance and low power consumption. Traditional high-voltage CMOS switches have on-resistance values of 50-200 Ohms; the iCMOS process achieves 4 Ohm, a 10-50x improvement.\n\nThe ADG1434 contains four independently controlled SPDT switches. Each SPDT switch has one common terminal (D) and two selectable terminals (S1, S2). The control input (INx) selects which terminal is connected to the common: when INx is LOW, S1A is connected to DA; when INx is HIGH, S1B is connected to DA. Each switch operates independently, and the four switches can be used to route four different signals simultaneously.\n\nThe 4 Ohm typical on-resistance is one of the lowest available for a plus or minus 15 V analog switch. This low on-resistance minimizes signal attenuation and voltage error when the switch is in the signal path. For example, with a 10 kOhm load, a 4 Ohm switch introduces only 0.04 percent voltage error (4 \/ 10004), which is negligible for most applications.\n\nThe on-resistance flatness of 0.5 Ohm is equally important. On-resistance varies with the analog signal voltage (because the MOSFET gate-source voltage changes as the analog signal swings), and this variation causes distortion. A 0.5 Ohm flatness means the on-resistance varies by only plus or minus 0.25 Ohm over the full analog signal range, resulting in very low distortion (0.06 percent THD+N). This is critical for audio and precision measurement applications.\n\nThe break-before-make (BBM) switching action ensures that the currently connected channel is disconnected before the new channel is connected, preventing momentary short circuits between the two signal sources. The BBM time delay is guaranteed to be at least 90 ns, which is sufficient to prevent short-circuit current spikes but short enough to minimize the signal glitch duration.\n\nThe very low leakage currents (0.02 nA typical off-leakage at 25 degrees C) ensure that signals on disconnected channels do not bleed through to the output. At 85 degrees C, the maximum off-leakage is only 3 nA, which for a 100 kOhm source impedance produces only 300 uV of crosstalk voltage - well below the noise floor of most measurement systems.\n\nThe plus or minus 15 V supply capability makes the ADG1434 suitable for professional audio equipment (which typically uses plus or minus 15 V analog supplies), industrial instrumentation, and data acquisition systems that need to switch signals with up to plus or minus 10 V amplitude. The device can also operate from a single plus 12 V supply (with GND = 0 V and VSS = 0 V) or from plus or minus 5 V supplies for lower-voltage systems.\n\nThe 200 MHz -3 dB bandwidth at plus or minus 15 V allows the switch to pass high-frequency signals without significant attenuation. Combined with the low on-resistance, this makes the ADG1434 suitable for video routing and high-speed data acquisition.\n\nThe ADG1434 is the quad SPDT version; the ADG1433 is the triple SPDT version with EN input, available in both TSSOP-16 and LFCSP-16. The ADG1434 in TSSOP-20 does not have an EN pin (all channels are always active); the LFCSP-20 version includes an EN pin. For applications requiring the EN function, use ADG1434YCPZ-REEL7 instead.\n\nThe -70 dB off-isolation at 1 MHz and -70 dB channel-to-channel crosstalk ensure excellent signal integrity when multiple channels are used simultaneously. These specifications degrade at higher frequencies but remain acceptable for most audio and instrumentation applications up to several MHz.","working_principle":"The ADG1434YRUZ-REEL7 operates as a set of four independently controlled SPDT analog switches using enhancement-mode N-channel and P-channel MOSFETs in a T-switch configuration, fabricated on the iCMOS process.\n\nSwitch Element: Each SPDT switch position uses a complementary NMOS\/PMOS pair connected in parallel. The NMOS transistor conducts the negative half of the analog signal, while the PMOS transistor conducts the positive half. Together, they provide rail-to-rail signal handling from VSS to VDD. The on-resistance of the NMOS and PMOS transistors varies in opposite directions with the analog signal voltage: as the signal rises toward VDD, the NMOS RDS(on) increases while the PMOS RDS(on) decreases. The parallel combination produces a relatively flat on-resistance characteristic over the signal range, resulting in the 0.5 Ohm flatness specification.\n\niCMOS Process: The iCMOS (industrial CMOS) process differs from standard CMOS by incorporating high-voltage DMOS (Double-diffused MOS) transistors that can withstand up to 33 V between drain and source. This enables the ADG1434 to operate at plus or minus 15 V supplies while maintaining low on-resistance. In a standard CMOS process, the MOSFET on-resistance increases dramatically with voltage rating due to the longer channel and heavier drift region required. The iCMOS process uses a lateral DMOS structure that separates the high-voltage blocking region from the channel region, achieving both high voltage capability and low on-resistance simultaneously.\n\nSwitch Control: Each SPDT switch has a control input (INx). The control logic is non-inverting: when INx is LOW (below 0.8 V), the A-side switch is closed (S1A connected to D1) and the B-side switch is open; when INx is HIGH (above 2.0 V), the B-side switch is closed (S1B connected to D1) and the A-side switch is open. The digital inputs are 3 V logic compatible, meaning they can be driven by 3.3 V logic even when the analog supplies are plus or minus 15 V. The level shifting is done internally.\n\nBreak-Before-Make: The BBM circuit ensures a minimum dead time (90 ns) between opening one switch and closing the other. During this dead time, the common terminal (D) is floating (high impedance). The BBM action prevents the two signal sources (S1A and S1B) from being momentarily connected together, which would cause current to flow from the higher voltage source to the lower voltage source, potentially damaging the source or causing signal glitches. The BBM time is controlled by an internal delay circuit.\n\nCharge Injection: When a MOSFET switch transitions from on to off, the gate charge that was inducing the channel must go somewhere, and a small amount (charge injection) is coupled to the analog signal path through the gate-to-channel capacitance. The ADG1434 has a charge injection of -10 pC at plus or minus 5 V. The negative sign indicates that the output voltage steps negative when the switch turns off. At plus or minus 15 V, the charge injection is typically -50 pC. The charge injection is relatively constant over the analog signal range, which means it can be partially compensated by adding an equal and opposite charge injection from a dummy switch driven by the complementary control signal.\n\nLeakage Currents: When a switch is off, the NMOS and PMOS transistors are both in cutoff, and only the subthreshold leakage and junction leakage currents flow. The 0.02 nA typical off-leakage at 25 degrees C is achieved by careful layout and process design to minimize junction areas and surface leakage paths. At 125 degrees C, the leakage increases due to the temperature dependence of the subthreshold current and junction reverse saturation current, but remains below 8 nA.\n\nBandwidth and Isolation: The -3 dB bandwidth of 145 MHz at plus or minus 5 V is determined by the RC time constant of the on-resistance (4 Ohm) and the off-state capacitance of the switch and PCB trace. The off-isolation (-70 dB at 1 MHz) is determined by the parasitic capacitance between the open switch terminal and the common terminal, which creates a capacitive voltage divider with the load impedance. At higher frequencies, the isolation degrades because the capacitive reactance decreases. The channel-to-channel crosstalk (-70 dB at 1 MHz) is determined by the parasitic capacitance between adjacent switch channels on the die and in the package.\n\nPower Dissipation: The ADG1434 draws very low supply current (IDD = 18 uA, ISS = 0.5 uA typical) for the internal logic and control circuits. The power dissipation is dominated by the load current through the on-resistance: P = I^2 x RON. At 115 mA per channel, the power dissipation per channel is 115^2 x 4 = 53 mW. With all four channels carrying 115 mA, total switch dissipation is 212 mW, plus the quiescent dissipation.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | S1A<\/td> | Analog I\/O<\/td> | Switch 1, A-side source terminal; when IN1 is LOW, S1A is connected to D1 (switch closed); when IN1 is HIGH, S1A is disconnected (switch open); signal range VSS to VDD; bidirectional; connect to signal source or destination depending on application<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 2<\/td> | D1<\/td> | Analog I\/O<\/td> | Switch 1, common (drain) terminal; the signal routing node that connects to either S1A or S1B depending on IN1 state; bidirectional; signal range VSS to VDD; this is typically the output of the multiplexer or the input to the demultiplexer<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 3<\/td> | S1B<\/td> | Analog I\/O<\/td> | Switch 1, B-side source terminal; when IN1 is HIGH, S1B is connected to D1 (switch closed); when IN1 is LOW, S1B is disconnected (switch open); signal range VSS to VDD; bidirectional<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 4<\/td> | S2A<\/td> | Analog I\/O<\/td> | Switch 2, A-side source terminal; controlled by IN2; same characteristics as S1A; independent of Switch 1<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 5<\/td> | D2<\/td> | Analog I\/O<\/td> | Switch 2, common (drain) terminal; same characteristics as D1; independent of Switch 1<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 6<\/td> | S2B<\/td> | Analog I\/O<\/td> | Switch 2, B-side source terminal; controlled by IN2; same characteristics as S1B<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 7<\/td> | GND<\/td> | Ground<\/td> | Digital ground reference; connect to system ground; the digital control inputs are referenced to GND; GND can be different from VSS (e.g., VSS = -15 V, GND = 0 V); the GND pin must be connected even if all control inputs are driven from 0\/5 V logic<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 8<\/td> | VSS<\/td> | Power<\/td> | Negative analog supply; -15 V typical for dual supply operation; -4.5 V to -16.5 V; connect to GND (0 V) for single supply operation; must not exceed VDD in voltage; bypass with 0.1 uF ceramic capacitor to GND near the pin<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 9<\/td> | IN4<\/td> | Digital Input<\/td> | Switch 4 control input; 3 V logic compatible; LOW selects A-side (S4A to D4); HIGH selects B-side (S4B to D4); VIH min 2.0 V; VIL max 0.8 V; can be driven by 3.3 V or 5 V logic; input current less than 0.1 uA<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 10<\/td> | S4A<\/td> | Analog I\/O<\/td> | Switch 4, A-side source terminal; controlled by IN4<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 11<\/td> | D4<\/td> | Analog I\/O<\/td> | Switch 4, common (drain) terminal; controlled by IN4<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 12<\/td> | S4B<\/td> | Analog I\/O<\/td> | Switch 4, B-side source terminal; controlled by IN4<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 13<\/td> | S3B<\/td> | Analog I\/O<\/td> | Switch 3, B-side source terminal; controlled by IN3<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 14<\/td> | D3<\/td> | Analog I\/O<\/td> | Switch 3, common (drain) terminal; controlled by IN3<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 15<\/td> | S3A<\/td> | Analog I\/O<\/td> | Switch 3, A-side source terminal; controlled by IN3<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 16<\/td> | IN3<\/td> | Digital Input<\/td> | Switch 3 control input; same specifications as IN4<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 17<\/td> | IN1<\/td> | Digital Input<\/td> | Switch 1 control input; same specifications as IN4<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 18<\/td> | VDD<\/td> | Power<\/td> | Positive analog supply; +15 V typical for dual supply; +4.5 V to +16.5 V; bypass with 0.1 uF ceramic capacitor to GND near the pin; for single supply operation, VDD is the positive supply and VSS connects to GND<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 19<\/td> | IN2<\/td> | Digital Input<\/td> | Switch 2 control input; same specifications as IN4<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 20<\/td> | GND<\/td> | Ground<\/td> | Digital ground reference; connect to system ground; both GND pins (7 and 20) must be connected externally<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|