The TPS54140DGQR from Texas Instruments is a 42V, 1.5A step-down (buck) DC\/DC converter with an integrated 200mohm high-side N-channel MOSFET in a 10-pin HVSSOP-EP (PowerPAD MSOP-10) package (3.0 x 3.0 mm). Input voltage range: 3.5V to 42V. Output voltage: adjustable from 0.8V to 39V via external resistor divider using the 0.8V internal reference. Current-mode control provides simple external compensation and flexible component selection. Switching frequency: adjustable from 100kHz to 2.5MHz via external resistor, or synchronizable to an external clock. Eco-mode pulse skipping reduces no-load quiescent current to 116uA. Shutdown current: 1.3uA. Adjustable UVLO via EN pin with 1.25V threshold. Slow start\/soft-start with adjustable timing or sequencing\/tracking via SS\/TR pin. Power-good output (open-drain) indicates output within 94%-107% of nominal. Integrated 200mohm high-side MOSFET supports up to 1.5A continuous output current. Frequency foldback and thermal shutdown protect during overload. Operating junction temperature: -40C to +150C. Active product, RoHS compliant, EAR99.<\/p>","protected":false},"excerpt":{"rendered":"
The TPS54140DGQR from Texas Instruments is a 42V, 1.5A step-down (buck) DC\/DC converter with an integrated 200mohm high-side N-channel MOSFET in a 10-pin HVSSOP-EP (PowerPAD MSOP-10) package (3.0 x 3.0 mm). Input voltage range: 3.5V to 42V. Output voltage: adjustable from 0.8V to 39V via external resistor divider using the 0.8V internal reference. Current-mode control […]<\/p>\n","protected":false},"author":2,"featured_media":2844,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[23,13],"tags":[],"chip_brand":[138],"class_list":["post-1918","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-data-conversion-ics-adc-dac","category-integrated-circuits-ics","chip_brand-ti"],"acf":{"brief_explanation":"42V, 1.5A buck DC-DC, 200mohm MOSFET, 100kHz-2.5MHz, Eco-mode 116uA IQ, adj UVLO, SS\/TR, PWRGD, MSOP-10-EP","date_code":"","package_case":"HVSSOP-EP \/ PowerPAD MSOP-10 (3.0 x 3.0 x 0.95 mm)","in_stock":6505,"datasheet":"https:\/\/www.ti.com\/product\/TPS54140A","price":"$0.237 (1K+ pcs)","product_introduction":"The TPS54140DGQR from Texas Instruments is a 42V, 1.5A step-down DC\/DC converter with an integrated high-side N-channel MOSFET, designed for industrial, automotive aftermarket, and general-purpose power supply applications. The device uses current-mode control with a wide switching frequency range (100kHz to 2.5MHz), allowing designers to optimize the trade-off between efficiency and external component size.\n\nThe TPS54140A is an improved version of the original TPS54140, featuring a tighter enable threshold for more accurate undervoltage lockout (UVLO) programming. Both versions share the same pinout, package, and most electrical characteristics, and the TPS54140A is recommended for new designs. The DGQR suffix indicates the HVSSOP-EP (PowerPAD MSOP-10) package in tape-and-reel packaging.\n\nKey features include a wide input voltage range (3.5V to 42V) that supports 12V and 24V industrial bus voltages with margin, a 200mohm integrated high-side MOSFET that delivers up to 1.5A continuous output current, and an adjustable output voltage from 0.8V to 39V using external resistors with a 0.8V internal reference. The wide output range allows the device to generate common logic voltages (1.8V, 2.5V, 3.3V, 5V) as well as intermediate voltages for specialized applications.\n\nThe Eco-mode pulse-skipping feature dramatically reduces quiescent current at light loads. When the output current drops below the Eco-mode threshold, the device enters a pulse-skipping mode where switching cycles are skipped to maintain regulation while minimizing switching losses. The no-load regulated supply current drops to 116uA, making the device suitable for always-on or standby power rails in battery-powered systems. When full PWM operation is needed for tight output voltage regulation or minimum output ripple, the Eco-mode can be defeated by keeping the load above the pulse-skipping threshold.\n\nThe adjustable switching frequency is set via an external resistor from the RT\/CLK pin to GND. Lower frequencies (100-500kHz) improve efficiency by reducing switching losses but require larger inductors and capacitors. Higher frequencies (1-2.5MHz) allow smaller external components but increase switching losses. The RT\/CLK pin also functions as a synchronization input, allowing the switching frequency to be synchronized to an external clock source. This is useful in systems with multiple converters where beat frequencies or electromagnetic interference (EMI) must be minimized.\n\nThe slow start (SS\/TR) pin provides adjustable output voltage ramp-up time, preventing inrush current surges during startup. The pin can also be configured for power supply sequencing or tracking, where the output voltage follows a master rail with a defined ratio. This is critical in systems with FPGAs, processors, or other devices that require specific power-on sequencing.\n\nThe power-good (PWRGD) output is an open-drain transistor that pulls LOW when the output voltage falls outside the 94%-107% window of the nominal setpoint. This signal can be used to enable downstream loads, trigger fault handlers, or daisy-chain multiple converters for sequential power-up. The PWRGD pin has a built-in filter to prevent false triggering during transient events.\n\nThe EN (enable) pin serves a dual purpose: it enables\/disables the converter, and it allows adjustable UVLO with hysteresis. The internal UVLO is set at 2.5V, but by connecting a resistor divider from VIN to EN, the UVLO threshold can be increased to any voltage up to 42V. The hysteresis is created by the difference between the EN rising threshold (1.25V) and falling threshold (1.11V), preventing chattering during slow input voltage ramps.","working_principle":"The TPS54140DGQR operates as a current-mode controlled step-down (buck) DC\/DC converter with an integrated high-side MOSFET.\n\nBuck Converter Topology: The basic buck converter consists of a high-side switch (integrated 200mohm N-channel MOSFET), an external LC output filter (inductor and capacitor), and a low-side switch (external Schottky diode or the body diode of the high-side MOSFET during dead time). During the ON-time, the high-side MOSFET conducts, connecting the input voltage to the inductor. The inductor current ramps up linearly at a rate of dI\/dt = (VIN - VOUT) \/ L, storing energy in the inductor's magnetic field. During the OFF-time, the high-side MOSFET turns off, and the inductor current freewheels through the external Schottky diode (catch diode). The inductor current ramps down at a rate of dI\/dt = VOUT \/ L, delivering stored energy to the output.\n\nCurrent-Mode Control: The TPS54140 uses peak current-mode control, where the error amplifier output (COMP pin voltage) sets the peak inductor current threshold for each switching cycle. The control loop operates as follows: (1) The output voltage is sensed via the VSENSE pin and compared to the 0.8V internal reference by the error amplifier. (2) The error amplifier output (COMP) represents the required peak inductor current. (3) At the start of each switching cycle, the high-side MOSFET turns on and the inductor current ramps up. (4) When the sensed current reaches the COMP threshold, the MOSFET turns off. (5) The cycle repeats at the next clock edge.\n\nCurrent-mode control provides several advantages over voltage-mode control: (1) The inductor current loop responds within one switching cycle to input voltage changes, providing excellent line transient response. (2) The control-to-output transfer function is first-order (vs second-order for voltage-mode), simplifying loop compensation. (3) The peak current is inherently limited by the COMP voltage, providing cycle-by-cycle overcurrent protection without additional circuitry. (4) Parallel operation of multiple converters is easier due to the current-sharing nature of current-mode control.\n\nExternal Compensation: The COMP pin allows external type-II or type-III compensation networks to be connected, giving the designer full control over the loop response. A simple type-II network (series RC from COMP to GND with a parallel capacitor) is sufficient for most applications with ceramic output capacitors. A type-III network adds a zero that can extend the bandwidth when using output capacitors with high ESR. The compensation component values depend on the crossover frequency, output capacitor ESR, inductor value, and load current range.\n\nEco-mode Operation: At light loads (typically below 50-100mA depending on inductor value and input voltage), the TPS54140 enters Eco-mode pulse skipping. In this mode, the converter delivers energy in single pulses separated by periods of no switching. The controller monitors the VSENSE voltage and initiates a switching pulse only when the output voltage drops below the regulation threshold. Between pulses, the high-side MOSFET is off and the inductor current is zero (discontinuous conduction mode). This eliminates the switching losses associated with continuous PWM operation, reducing the no-load supply current to 116uA. The trade-off is increased output voltage ripple (typically 10-30mV) and a lower crossover frequency in Eco-mode.\n\nFrequency Foldback: During an overload or short-circuit condition, the switching frequency is reduced (folded back) from the nominal setting to a minimum of approximately 33kHz. This limits the maximum current that can build up in the inductor during each cycle, protecting the MOSFET and the catch diode from excessive power dissipation. The foldback ratio depends on the output voltage: as VOUT decreases, the frequency decreases proportionally. When the overload is removed, the frequency returns to normal.\n\nThermal Shutdown: If the junction temperature exceeds approximately 165C, the thermal shutdown circuit disables the converter. The converter restarts when the junction temperature drops below approximately 150C (15C hysteresis). This protects the device from permanent damage due to excessive power dissipation. The thermal shutdown is not intended as a normal operating feature; proper thermal design should ensure that the junction temperature remains well below the shutdown threshold under worst-case conditions.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | BOOT<\/td> | Power<\/td> | Bootstrapped supply for high-side MOSFET gate driver; connect a 0.1uF ceramic capacitor from BOOT to PH; the capacitor is charged from VCC through an internal diode during the OFF-time of the high-side MOSFET<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 2<\/td> | VIN<\/td> | Power<\/td> | Input supply voltage; 3.5V to 42V; connect to input power rail through a pi-filter or decouple with 0.1uF + 10uF ceramic capacitors to GND; high-frequency decoupling is critical for reducing input ripple and EMI<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 3<\/td> | VIN<\/td> | Power<\/td> | Input supply voltage (second pin); internally connected to Pin 2; connect both VIN pins to the input power plane; provides low-impedance path for the high-side MOSFET drain current<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 4<\/td> | VSENSE<\/td> | Input<\/td> | Output voltage feedback input; connect to output voltage through a resistor divider; the internal error amplifier compares VSENSE to the 0.8V reference; divider ratio sets the output voltage: VOUT = 0.8V x (1 + Rtop\/Rbottom); keep PCB traces short and away from switching nodes to minimize noise pickup<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 5<\/td> | EN<\/td> | Input<\/td> | Enable and adjustable UVLO input; internal pull-up current source (1.2uA) holds EN HIGH when floating (converter enabled); drive LOW to disable; connect resistor divider from VIN to EN to GND for adjustable UVLO threshold; rising threshold = 1.25V, falling threshold = 1.11V (built-in hysteresis)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 6<\/td> | SS\/TR<\/td> | I\/O<\/td> | Slow start and tracking input; connect a capacitor from SS\/TR to GND to set the startup ramp time (tss = Css x 0.8V \/ 2.3uA); the output ramps up at the same rate as the SS\/TR voltage; can also be driven by an external voltage for tracking or sequencing; during fault conditions, SS\/TR is discharged to restart the soft-start sequence<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 7<\/td> | COMP<\/td> | Output<\/td> | Error amplifier output; connect external compensation network (type-II or type-III) from COMP to GND; the compensation network sets the control loop crossover frequency and phase margin; do not leave COMP pin floating<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 8<\/td> | GND<\/td> | Power<\/td> | Signal ground; internal reference for control circuitry; connect to PCB ground plane with low-impedance path; keep separate from power ground (PGND) traces carrying high switching currents<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 9<\/td> | GND<\/td> | Power<\/td> | Power ground; return path for gate driver and internal bias circuits; connect to PCB ground plane; must have low-impedance connection to input and output capacitor ground terminals<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 10<\/td> | PH<\/td> | Power<\/td> | Phase node (switching node); connects to the source of the integrated high-side MOSFET and the anode of the external catch diode; connect the output inductor and catch diode to this pin; minimize PCB trace length and copper area to reduce EMI; do not route sensitive signals near this node<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| EP<\/td> | PowerPAD<\/td> | Power<\/td> | Exposed thermal pad; electrically connected to GND internally; must be soldered to PCB copper pour for proper thermal dissipation; connect to ground plane through thermal vias; critical for junction-to-PCB thermal resistance<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|