The PIC18F67K40-I\/PT from Microchip Technology is a 64-pin, low-power, high-performance 8-bit microcontroller with XLP (eXtreme Low Power) technology in a 64-lead TQFP package (10x10mm, 0.5mm pitch). Key features: PIC18 enhanced core at up to 64MHz (16 MIPS), 128KB Flash program memory, 3562 bytes SRAM, 1024 bytes EEPROM, 60 I\/O pins, 47-channel 10-bit ADC, 1x 5-bit DAC, 3 comparators, 2x I2C\/SPI, 5x EUSART with LIN, 5x 8-bit timers, 4x 16-bit timers, 2x standalone 10-bit PWM, 5x CCP modules, 1x Complementary Waveform Generator (CWG), 1x Zero-Cross Detect (ZCD), 1x CRC with Memory Scan, 2x Signal Measurement Timer (SMT), 1x Hardware Limit Timer (HLT), Windowed Watchdog Timer (WWDT), Peripheral Pin Select (PPS), Hardware Capacitive Voltage Divider (CVD) for mTouch. Operating voltage: 2.3V to 5.5V (LF variant: 1.8V to 3.6V). XLP: Sleep mode 50nA @ 1.8V, Active mode 32uA\/MHz @ 1.8V. Industrial temperature range: -40C to 85C. Functional safety ready (IEC 61508, ISO 26262). RoHS compliant.<\/p>","protected":false},"excerpt":{"rendered":"
The PIC18F67K40-I\/PT from Microchip Technology is a 64-pin, low-power, high-performance 8-bit microcontroller with XLP (eXtreme Low Power) technology in a 64-lead TQFP package (10x10mm, 0.5mm pitch). Key features: PIC18 enhanced core at up to 64MHz (16 MIPS), 128KB Flash program memory, 3562 bytes SRAM, 1024 bytes EEPROM, 60 I\/O pins, 47-channel 10-bit ADC, 1x 5-bit […]<\/p>\n","protected":false},"author":2,"featured_media":2849,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,25],"tags":[],"chip_brand":[134],"class_list":["post-1909","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-integrated-circuits-ics","category-microcontrollers-mcu","chip_brand-microchip"],"acf":{"brief_explanation":"PIC18 8-bit MCU, 128KB Flash, 3562B RAM, 1KB EEPROM, 60 I\/O, 47-ch 10-bit ADC, 5x EUSART, XLP, 64-TQFP, -40~85C","date_code":"","package_case":"64-Lead TQFP (PT Package) (10 x 10 x 1.2 mm, 0.5mm pitch)","in_stock":8420,"datasheet":"https:\/\/www.microchip.com\/en-us\/product\/PIC18F67K40","price":"$4.28 (1K+ pcs)","product_introduction":"The PIC18F67K40-I\/PT from Microchip Technology is a 64-pin, high-performance 8-bit microcontroller from the PIC18 K40 family, featuring eXtreme Low Power (XLP) technology. The device combines large memory resources with an extensive peripheral set in a compact 64-lead TQFP package, targeting general-purpose embedded control applications that require rich analog integration, flexible communication interfaces, and low power consumption.\n\nThe PIC18 K40 family represents a significant evolution over the classic PIC18F series, introducing Core Independent Peripherals (CIPs) that can operate without CPU intervention, reducing CPU overhead and enabling more efficient system designs. Key CIPs include the Complementary Waveform Generator (CWG) for half-bridge and full-bridge motor drive, the CRC with Memory Scan for data integrity verification, the Hardware Capacitive Voltage Divider (CVD) for capacitive touch sensing, and the Signal Measurement Timer (SMT) for precise pulse and period measurements.\n\nMemory resources are substantial: 128KB of Flash program memory (supporting self read\/write for bootloader and data logging), 3562 bytes of SRAM (sufficient for complex data buffering and DSP algorithms), and 1024 bytes of data EEPROM (for calibration data and configuration parameters that must survive power cycles). The 128KB Flash can hold approximately 65,000 instructions, providing ample space for complex application code.\n\nAnalog capabilities are extensive: a 47-channel 10-bit ADC with multiple acquisition modes (including Hardware CVD for touch sensing), a 5-bit DAC for voltage reference generation or simple analog output, 3 analog comparators with configurable hysteresis, and a Fixed Voltage Reference (FVR) module providing 1.024V, 2.048V, and 4.096V reference levels. The Hardware CVD (Capacitive Voltage Divider) enables mTouch capacitive sensing without external components, supporting buttons, sliders, and wheels.\n\nCommunication interfaces include 5 EUSART modules with LIN bus support (ideal for automotive and industrial networking), 2 independent I2C\/SPI modules (supporting both master and slave modes), and Peripheral Pin Select (PPS) that allows flexible remapping of digital peripheral functions to any of the 60 I\/O pins. PPS dramatically simplifies PCB layout by allowing signals to be routed to the most convenient pins.\n\nTimer resources include 5 x 8-bit timers, 4 x 16-bit timers, 2 x Signal Measurement Timers (SMT) for pulse width, period, and duty cycle measurement, and 1 x Hardware Limit Timer (HLT) that can generate periodic interrupts even in Sleep mode. PWM outputs include 2 standalone 10-bit PWM modules and 5 CCP (Capture\/Compare\/PWM) modules.\n\nXLP technology enables extremely low power consumption: Sleep mode draws only 50nA at 1.8V (typical), Active mode draws 32uA\/MHz at 1.8V, and the Low-Power Brown-Out Reset (LPBOR) consumes minimal current. The device supports multiple power-saving modes: Sleep (CPU and most peripherals stopped), Idle (CPU stopped, selected peripherals running), and Doze (CPU clock divided down, peripherals at full speed).\n\nThe -I\/PT suffix indicates: I = Industrial temperature range (-40C to 85C); PT = 64-lead TQFP package. An Extended temperature variant (-E\/PT, -40C to 125C) is also available for automotive applications. The device is functional safety ready, with documentation (FMEDA report and Safety Manual) available on request for IEC 61508 and ISO 26262 certifications.","working_principle":"The PIC18F67K40-I\/PT operates as an enhanced 8-bit PIC18 microcontroller with XLP technology and Core Independent Peripherals.\n\nPIC18 Enhanced Core: The CPU implements the PIC18 enhanced instruction set with 83 instructions (up from 75 in classic PIC18), supporting 31 levels of hardware stack. The instruction word is 16 bits wide, and most instructions execute in a single cycle (2 clock periods). At the maximum 64MHz internal oscillator frequency, instruction execution rate is 16 MIPS. The core includes an 8x8 hardware multiplier for single-cycle multiplication, and supports both direct and indirect addressing with access RAM for fast variable access.\n\nOscillator Module: The internal oscillator block provides a 64MHz high-frequency oscillator (HFINTOSC) and a 64kHz low-frequency oscillator (LFINTOSC), eliminating the need for external crystals in most applications. The HFINTOSC can be tuned via the OSCTUNE register for precise timing. External oscillator modes (EC, LP, XT, HS) are also supported for applications requiring crystal accuracy. A Fail-Safe Clock Monitor (FSCM) detects external oscillator failure and automatically switches to the internal oscillator.\n\nPeripheral Pin Select (PPS): The PPS module allows most digital peripheral input and output functions to be mapped to any of the available I\/O pins through software configuration. This eliminates the pin-function constraints of fixed-peripheral devices and dramatically simplifies PCB routing. Each digital peripheral (UART TX\/RX, SPI SCK\/SDI\/SDO, I2C SDA\/SCL, CCP output, PWM output, etc.) has a corresponding PPS output or input selection register.\n\nCore Independent Peripherals (CIPs): CIPs can operate autonomously without CPU intervention, enabling the device to handle complex real-time tasks with minimal software overhead. Key CIPs include: (1) CWG (Complementary Waveform Generator) - generates complementary PWM signals with programmable dead band for half-bridge and full-bridge motor drive; (2) CRC with Memory Scan - performs CRC calculations on Flash and RAM for data integrity; (3) SMT (Signal Measurement Timer) - measures pulse width, period, and duty cycle of external signals with 16-bit or 32-bit resolution; (4) HLT (Hardware Limit Timer) - generates periodic interrupts even in Sleep mode for wake-up timing; (5) ZCD (Zero-Cross Detect) - detects AC line zero crossings for TRIAC dimming and power control.\n\nHardware CVD (Capacitive Voltage Divider): The CVD module enables capacitive touch sensing using the ADC without external components. It works by charging an internal sample capacitor and then connecting it to an external sensor pad through a voltage divider, measuring the charge transfer. The CVD can detect capacitance changes as small as a few picofarads, sufficient for finger touch detection on buttons, sliders, and wheels.\n\nXLP Power Management: The XLP architecture minimizes power consumption through: (1) Optimized transistor-level design for low leakage; (2) Multiple power domains that can be independently enabled\/disabled; (3) Low-Power BOR (LPBOR) that monitors VDD at microamp current levels; (4) Sleep mode (50nA) where the CPU and most peripherals are stopped but selected peripherals (WDT, RTCC, SMT) can continue operating; (5) Idle mode where the CPU is stopped but enabled peripherals continue; (6) Doze mode where the CPU clock is divided down (by 1 to 128) while peripheral clocks remain at full speed, reducing CPU power consumption during less compute-intensive periods.\n\nADC Module: The 10-bit ADC supports 47 input channels with multiple acquisition modes: individual channel, continuous acquisition, and CVD mode. The ADC can be triggered by multiple sources including timers, PWM events, and software. The conversion time is approximately 2us at the maximum acquisition rate, providing up to 500Ksps throughput. The FVR module provides stable voltage references for accurate ADC measurements independent of VDD variations.\n\nFunctional Safety: The device is designed to support functional safety applications per IEC 61508 (industrial) and ISO 26262 (automotive). Key safety features include: CRC\/Memory Scan for detecting Flash and RAM corruption, Windowed Watchdog Timer (WWDT) for detecting software hangs, Clock Fail-Safe Monitor (FSCM) for detecting oscillator failures, and Brown-Out Reset (BOR) for detecting supply voltage drops. Microchip provides FMEDA reports and Safety Manuals on request.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | RE1<\/td> | I\/O<\/td> | Port E bit 1; general-purpose I\/O; PPS capable; can be remapped to digital peripheral functions<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 2<\/td> | RE0<\/td> | I\/O<\/td> | Port E bit 0; general-purpose I\/O; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 3<\/td> | RG0<\/td> | I\/O<\/td> | Port G bit 0; general-purpose I\/O; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 4<\/td> | RG1<\/td> | I\/O<\/td> | Port G bit 1; general-purpose I\/O; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 5<\/td> | RG2<\/td> | I\/O<\/td> | Port G bit 2; general-purpose I\/O; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 6<\/td> | RG3<\/td> | I\/O<\/td> | Port G bit 3; general-purpose I\/O; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 7<\/td> | VPP\/MCLR\/RG5<\/td> | Input\/I\/O<\/td> | Master Clear (reset) input; active LOW; also serves as VPP during programming; internal pull-up; can be configured as RG5 digital I\/O via MCLRE configuration bit<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 8<\/td> | RG4<\/td> | I\/O<\/td> | Port G bit 4; general-purpose I\/O; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 9<\/td> | VSS<\/td> | Power<\/td> | Ground; connect all VSS pins together to system ground plane<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 10<\/td> | VDD<\/td> | Power<\/td> | Positive supply; 2.3V to 5.5V; decouple with 0.1uF ceramic capacitor to VSS; connect all VDD pins together<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 11-16<\/td> | RF7-RF2<\/td> | I\/O<\/td> | Port F bits 7-2; general-purpose I\/O; PPS capable; each pin individually configurable as input or output<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 17-22<\/td> | RC2-RC7<\/td> | I\/O<\/td> | Port C bits 2-7; general-purpose I\/O; PPS capable; alternate functions include EUSART, SPI, I2C, CCP, PWM depending on PPS configuration<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 23-28<\/td> | RD7-RD2<\/td> | I\/O<\/td> | Port D bits 7-2; general-purpose I\/O; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 29-32<\/td> | RD1-RD0,RC1,RC0<\/td> | I\/O<\/td> | Port D bits 1-0 and Port C bits 1-0; general-purpose I\/O; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 33-40<\/td> | RA0-RA7<\/td> | I\/O<\/td> | Port A bits 0-7; mixed analog and digital I\/O; RA0-RA3 serve as ADC inputs; RA5 can be T0CKI; RA6 and RA7 can be oscillator pins; PPS capable on digital functions<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 41-48<\/td> | RB0-RB7<\/td> | I\/O<\/td> | Port B bits 0-7; general-purpose I\/O; PPS capable; RB0-RB7 have interrupt-on-change capability; RB5 also serves as ICSP programming clock (PGC); RB6 as ICSP data (PGD)<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 49-53<\/td> | RE2,RD3-RD6<\/td> | I\/O<\/td> | Port E bit 2 and Port D bits 3-6; general-purpose I\/O; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 54-56<\/td> | RF0-RF1,RD0<\/td> | I\/O<\/td> | Port F bits 0-1 and Port D bit 0; general-purpose I\/O; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 57<\/td> | RF3<\/td> | I\/O<\/td> | Port F bit 3; PPS capable; also SCL2\/SDA2 alternate when configured<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 58<\/td> | RF4<\/td> | I\/O<\/td> | Port F bit 4; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 59<\/td> | RF5<\/td> | I\/O<\/td> | Port F bit 5; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 60<\/td> | RB5\/PGC<\/td> | I\/O<\/td> | Port B bit 5; also ICSP programming clock; interrupt-on-change capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 61<\/td> | RB4<\/td> | I\/O<\/td> | Port B bit 4; interrupt-on-change capable; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 62<\/td> | RB3<\/td> | I\/O<\/td> | Port B bit 3; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 63<\/td> | RB2<\/td> | I\/O<\/td> | Port B bit 2; PPS capable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 64<\/td> | RB1<\/td> | I\/O<\/td> | Port B bit 1; PPS capable<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|