El MMA8653FCR1 de NXP Semiconductors es un aceler\u00f3metro MEMS digital de 3 ejes y 10 bits en un compacto encapsulado DFN-10 (2x2x1 mm). Presenta rangos de escala completa seleccionables din\u00e1micamente de m\u00e1s\/menos 2g, m\u00e1s\/menos 4g y m\u00e1s\/menos 8g con una sensibilidad de 1 mg\/LSB y un bajo ruido de 150 micro-g por ra\u00edz-Hz. El dispositivo se comunica a trav\u00e9s de I2C (direcci\u00f3n de 7 bits 0x1D) y admite los modos est\u00e1ndar (100 kHz) y r\u00e1pido (400 kHz), con velocidades de salida de datos de 1,56 Hz a 800 Hz. Las funciones integradas incluyen detecci\u00f3n de movimiento configurable, detecci\u00f3n de ca\u00edda libre y detecci\u00f3n de orientaci\u00f3n vertical\/horizontal, todas ellas accesibles a trav\u00e9s de dos pines de interrupci\u00f3n programables (INT1, INT2). La funci\u00f3n Auto-Wake\/Sleep cambia autom\u00e1ticamente la ODR en funci\u00f3n de la actividad, lo que permite un consumo de corriente ultrabajo de 7 microamperios en modo de bajo consumo. Tensi\u00f3n de alimentaci\u00f3n: de 1,95 V a 3,6 V; tensi\u00f3n de la interfaz I2C: de 1,62 V a 3,6 V. Temperatura de funcionamiento: -40C a 85C. Estado: Obsoleto (NXP recomienda FXLS8974CF como sustituto). RoHS3, EAR99.<\/p>","protected":false},"excerpt":{"rendered":"
The MMA8653FCR1 from NXP Semiconductors is a 3-axis, 10-bit digital MEMS accelerometer in a compact DFN-10 (2x2x1mm) package. It features dynamically selectable full-scale ranges of plus\/minus 2g, plus\/minus 4g, and plus\/minus 8g with 1 mg\/LSB sensitivity and low noise of 150 micro-g per root-Hz. The device communicates via I2C (7-bit address 0x1D) supporting standard mode […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,45,42],"tags":[],"chip_brand":[168],"class_list":["post-1897","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-motion-sensors","category-sensors","chip_brand-nxp"],"acf":{"brief_explanation":"3-axis 10-bit digital MEMS accelerometer, +\/-2g\/4g\/8g, I2C, 7uA low-power, DFN-10 (2x2mm), -40~85C, Obsolete","date_code":"","package_case":"DFN-10 (2 x 2 x 1.0 mm), Case 2162","in_stock":306,"datasheet":"https:\/\/www.nxp.com\/docs\/en\/data-sheet\/MMA8653FC.pdf","price":"$1.10 (3K+ pcs, LCSC)","product_introduction":"The MMA8653FCR1 from NXP Semiconductors is an intelligent, low-power, 3-axis capacitive MEMS accelerometer with 10-bit resolution, housed in an ultra-compact DFN-10 package measuring just 2 x 2 x 1.0 mm. The device is designed for consumer electronics and industrial sensing applications requiring motion, tilt, and orientation detection with minimal power consumption and board footprint.\n\nThe accelerometer features three dynamically selectable full-scale ranges: plus\/minus 2g (sensitivity 256 LSB\/g), plus\/minus 4g (128 LSB\/g), and plus\/minus 8g (64 LSB\/g), all with 1 mg\/LSB high sensitivity and low noise of 150 micro-g per root-Hz independent of resolution. The 10-bit ADC provides digital output accessible through an I2C serial interface at standard (100 kHz) or fast mode (400 kHz) data rates, with programmable output data rates from 1.56 Hz to 800 Hz.\n\nThe device is packed with embedded intelligent functions that offload the host processor: motion\/freefall detection, portrait\/landscape orientation detection with 15-degree hysteresis, and configurable auto-wake\/sleep state transitions. Two programmable interrupt pins (INT1, INT2) can be configured for any combination of embedded functions, enabling the accelerometer to monitor inertial events while remaining in a low-power mode during periods of inactivity. The auto-wake feature automatically increases the ODR when motion is detected and reduces it during inactivity, achieving an ultra-low 7 micro-amp current consumption in low-power mode.\n\nThe device operates with separate supply domains: VDD (1.95V to 3.6V) for the analog\/sensor section and VDDIO (1.62V to 3.6V) for the digital I2C interface, enabling direct connection to 1.8V, 2.5V, or 3.3V microcontrollers without level shifters. The BYP pin provides connection for the internal regulator bypass capacitor. The I2C slave address is 0x1D (write: 0x3A, read: 0x3B).\n\nThe R1 suffix denotes tape and reel packaging with 3,000 units per reel. Note: NXP has discontinued this product (End of Life) and recommends the FXLS8974CF as a replacement. The device is RoHS3 compliant, MSL Level 1 (unlimited), and classified as EAR99.","working_principle":"The MMA8653FCR1 operates as a capacitive MEMS accelerometer, converting mechanical acceleration into digital output through a transducer, signal conditioning, and analog-to-digital conversion pipeline.\n\nCapacitive Sensing Element: The core sensing mechanism uses a micro-electromechanical system (MEMS) structure consisting of a proof mass suspended by silicon springs above fixed electrodes. When acceleration is applied along any axis, the proof mass deflects proportionally, changing the capacitance between the proof mass and the fixed electrodes. The device contains three independent capacitive half-bridges, one for each axis (X, Y, Z), each producing a differential capacitance change proportional to the applied acceleration.\n\nSignal Conditioning: The capacitance changes are converted to voltage signals by a capacitance-to-voltage (C-V) converter using a switched-capacitor architecture. The voltage signals then pass through a programmable gain amplifier (PGA) that sets the full-scale range: plus\/minus 2g, plus\/minus 4g, or plus\/minus 8g. Higher gain increases sensitivity but reduces the maximum measurable acceleration range.\n\nAnalog-to-Digital Conversion: The conditioned analog signals are digitized by a 10-bit successive approximation register (SAR) ADC. The ADC operates at an oversampled rate, and the digital output is decimated to the user-selected output data rate (ODR) ranging from 1.56 Hz to 800 Hz. The 10-bit resolution provides 1,024 discrete levels, yielding 1 mg\/LSB sensitivity at the plus\/minus 2g range.\n\nDigital Signal Processing: The digitized acceleration data passes through a digital filter chain that includes both low-pass and high-pass filtering options. The high-pass filter removes the DC gravity component, enabling detection of dynamic acceleration events (motion, shock) without the static 1g gravity offset. The filtered data is stored in output registers accessible via the I2C interface.\n\nEmbedded Functions: The integrated state machines implement motion detection by comparing acceleration magnitude against programmable thresholds, freefall detection by checking if all-axis magnitude drops below a threshold, and orientation detection by analyzing the angle of the gravity vector relative to the device axes. These functions operate autonomously without host processor intervention, generating interrupts only when configured conditions are met.\n\nAuto-Wake\/Sleep: The power management state machine monitors accelerometer data and automatically transitions between active (high ODR) and sleep (low ODR) modes. When motion exceeding a configurable threshold is detected, the device wakes to a higher ODR for precise measurement. During periods of inactivity, the device sleeps at a lower ODR, reducing current consumption to as low as 7 micro-amps while still monitoring for wake events.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | VDD<\/td> | Power<\/td> | Device power supply (1.95V to 3.6V); connect 0.1uF and 1uF decoupling capacitors as close as possible to pin; powers the analog\/sensor section<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 2<\/td> | SCL<\/td> | Input<\/td> | I2C serial clock; open-drain, requires external pullup resistor to VDDIO; supports 100 kHz standard mode and 400 kHz fast mode; not tolerant above VDDIO+0.3V<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 3<\/td> | INT1<\/td> | Output<\/td> | Configurable interrupt output 1; can be mapped to any combination of embedded functions (motion, freefall, orientation, data ready, auto-wake\/sleep); active state polarity programmable<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 4<\/td> | BYP<\/td> | Output<\/td> | Internal regulator output bypass; connect a 0.1uF capacitor from BYP to GND for internal voltage regulator stability; do not connect external loads<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 5<\/td> | INT2<\/td> | Output<\/td> | Configurable interrupt output 2; independent from INT1; same mapping capabilities; enables monitoring two event categories on separate pins<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 6<\/td> | GND<\/td> | Power<\/td> | Ground; connect to system ground plane<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 7<\/td> | GND<\/td> | Power<\/td> | Ground; connect to system ground plane<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 8<\/td> | VDDIO<\/td> | Power<\/td> | Digital interface power supply (1.62V to 3.6V); sets the I2C and interrupt pin voltage levels; can differ from VDD for mixed-voltage systems; connect 0.1uF decoupling capacitor<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 9<\/td> | GND<\/td> | Power<\/td> | Ground; connect to system ground plane<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 10<\/td> | SDA<\/td> | I\/O<\/td> | I2C serial data; open-drain bidirectional, requires external pullup resistor to VDDIO; data latched on SCL rising edge; not tolerant above VDDIO+0.3V<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|