The SN74LVC138APWR from Texas Instruments is a 3-line to 8-line decoder\/demultiplexer in a 16-pin TSSOP package, designed for high-performance memory decoding and data routing applications. The device features three binary-weighted address inputs (A0, A1, A2) that select one of eight active-low outputs (Y0-Y7). Three enable inputs (two active-low G2A, G2B and one active-high G1) provide flexible cascading for expansion to 24-line or 32-line decoders without external inverters. Operating voltage: 1.65V to 3.6V, with 5V-tolerant inputs for mixed-voltage systems. Maximum propagation delay: 5.8ns at 3.3V. Output drive: plus\/minus 24mA. Quiescent current: 10uA max. Latch-up exceeds 250mA per JESD 17. -40C to 85C. MSL-1, RoHS, EAR99. Tape and reel, 2000\/reel.<\/p>","protected":false},"excerpt":{"rendered":"
The SN74LVC138APWR from Texas Instruments is a 3-line to 8-line decoder\/demultiplexer in a 16-pin TSSOP package, designed for high-performance memory decoding and data routing applications. The device features three binary-weighted address inputs (A0, A1, A2) that select one of eight active-low outputs (Y0-Y7). Three enable inputs (two active-low G2A, G2B and one active-high G1) provide […]<\/p>\n","protected":false},"author":2,"featured_media":2792,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,15],"tags":[],"chip_brand":[138],"class_list":["post-1891","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-integrated-circuits-ics","category-logic-chips","chip_brand-ti"],"acf":{"brief_explanation":"3-to-8 line decoder\/demultiplexer, 1.65-3.6V, 5V-tolerant inputs, 5.8ns tpd, TSSOP-16, -40~85C","date_code":"","package_case":"TSSOP-16 (PW) (5.0 x 4.4 x 1.05 mm)","in_stock":15876,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74lvc138a.pdf","price":"$0.21 (1K+ pcs)","product_introduction":"The SN74LVC138APWR from Texas Instruments is a 3-line to 8-line decoder\/demultiplexer housed in a 16-pin TSSOP package, designed for high-performance memory decoding and data routing applications requiring very short propagation delay times.\n\nThe device features three binary-weighted address inputs (A0, A1, A2) that select one of eight mutually exclusive active-low outputs (Y0 through Y7). Three enable inputs provide flexible control: two active-low enables (G2A, G2B) and one active-high enable (G1). The decoder is enabled only when G1 is HIGH and both G2A and G2B are LOW. When disabled, all outputs are forced HIGH regardless of the address inputs.\n\nThe multiple enable inputs facilitate easy cascading for address expansion. Four SN74LVC138A devices plus one inverter can implement a 1-of-32 (5-to-32 line) decoder without additional logic. A single enable input can also serve as a data input for demultiplexing applications, distributing a single data stream to one of eight output lines.\n\nKey specifications include: supply voltage 1.65V to 3.6V (single supply), 5.5V-tolerant inputs enabling use as a 3.3V-to-5V logic translator, maximum propagation delay of 5.8ns at 3.3V, output drive current of plus\/minus 24mA, maximum quiescent current of 10uA, and latch-up performance exceeding 250mA per JESD 17. The typical output ground bounce is less than 0.8V and output VOH undershoot exceeds 2V at VCC=3.3V.\n\nThe LVC (Low-Voltage CMOS) technology provides the optimal combination of high speed, low power, and wide voltage compatibility. The 74LVC138A is functionally identical to the industry-standard 74LS138 and 74HC138 but with broader voltage range and 5V-tolerant inputs. The PW suffix denotes TSSOP-16 package, R suffix denotes tape and reel with 2,000 units per reel. The device is RoHS compliant, MSL Level 1, EAR99 classified.","working_principle":"The SN74LVC138APWR operates as a combinational logic decoder that converts a 3-bit binary address into one-of-eight active-low output selections, with enable inputs for cascading and demultiplexing.\n\nDecoding Logic: The three address inputs A0 (LSB), A1, and A2 (MSB) form a 3-bit binary number from 0 to 7. Internally, the device implements eight 3-input AND gates, each fed by a unique combination of the address inputs (or their complements). For address value N, the corresponding output YN is driven LOW while all other outputs remain HIGH. Since all outputs are active-low, the selected output is the one that goes LOW. For example, if A2=0, A1=1, A0=0 (binary 010 = decimal 2), output Y2 goes LOW while Y0, Y1, Y3-Y7 remain HIGH.\n\nEnable Logic: The three enable inputs (G1, G2A, G2B) gate all eight output AND gates. The decoder is enabled only when G1=HIGH AND G2A=LOW AND G2B=LOW. If any enable condition is not met, all eight outputs are forced HIGH regardless of the address inputs. The enable logic expression is: Enable = G1 AND (NOT G2A) AND (NOT G2B). The dual active-low enables (G2A, G2B) are particularly useful for cascading: one can serve as a chip select from higher-order address lines while the other provides system-level enable\/disable control.\n\nCascading for Address Expansion: To build a 1-of-16 decoder, two SN74LVC138A devices are used. The most significant address bit (A3) connects to the enable inputs: one decoder is enabled when A3=0 (via G2A), and the other when A3=1 (via G1). For a 1-of-32 decoder, four devices are cascaded using a fifth address bit (A4) to select one of four decoder enable combinations. Two active-low enables and one active-high enable provide maximum flexibility in cascading configurations without requiring external inverters.\n\nDemultiplexing Mode: When used as a demultiplexer, one of the enable inputs serves as the data input. For example, connecting the serial data stream to G1 while keeping G2A=G2B=LOW routes the data to the output selected by the current address. When the data input is HIGH, the selected output goes LOW (active); when LOW, all outputs go HIGH. This provides 1-to-8 data distribution under address control.\n\n5V-Tolerant Inputs: The LVC family inputs can accept voltages up to 5.5V regardless of the VCC supply level. This enables the device to translate between 3.3V and 5V logic systems: a 5V microcontroller can drive the address and enable inputs of a 3.3V-supplied SN74LVC138A without level shifters. The output levels are determined by VCC, so the decoded outputs will be 3.3V logic levels.","pin_description":"
| Pin<\/th> | Name<\/th> | Type<\/th> | Description<\/th><\/tr><\/thead> | ||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1<\/td> | A0<\/td> | Input<\/td> | Address input LSB; 5.5V tolerant; selects output line Y0-Y7 based on 3-bit binary value<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 2<\/td> | A1<\/td> | Input<\/td> | Address input middle bit; 5.5V tolerant; combines with A0 and A2 to select active output<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 3<\/td> | A2<\/td> | Input<\/td> | Address input MSB; 5.5V tolerant; determines which group of four outputs (Y0-3 or Y4-7) is active<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 4<\/td> | \/G2A<\/td> | Input<\/td> | Active-low enable input; decoder active only when G2A=LOW, G2B=LOW, and G1=HIGH simultaneously<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 5<\/td> | \/G2B<\/td> | Input<\/td> | Active-low enable input; can serve as chip select or data input for demultiplexing; 5.5V tolerant<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 6<\/td> | G1<\/td> | Input<\/td> | Active-high enable input; decoder enabled when HIGH with both G2A and G2B LOW; 5.5V tolerant<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 7<\/td> | \/Y7<\/td> | Output<\/td> | Active-low decoded output 7; selected when A2A1A0 = 111; sinks up to 24mA<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 8<\/td> | GND<\/td> | Power<\/td> | Ground; connect to system ground plane<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 9<\/td> | \/Y6<\/td> | Output<\/td> | Active-low decoded output 6; selected when A2A1A0 = 110<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 10<\/td> | \/Y5<\/td> | Output<\/td> | Active-low decoded output 5; selected when A2A1A0 = 101<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 11<\/td> | \/Y4<\/td> | Output<\/td> | Active-low decoded output 4; selected when A2A1A0 = 100<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 12<\/td> | \/Y3<\/td> | Output<\/td> | Active-low decoded output 3; selected when A2A1A0 = 011<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 13<\/td> | \/Y2<\/td> | Output<\/td> | Active-low decoded output 2; selected when A2A1A0 = 010<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 14<\/td> | \/Y1<\/td> | Output<\/td> | Active-low decoded output 1; selected when A2A1A0 = 001<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 15<\/td> | \/Y0<\/td> | Output<\/td> | Active-low decoded output 0; selected when A2A1A0 = 000<\/td><\/tr> | ||||||||||||||||||||||||||||||||||||
| 16<\/td> | VCC<\/td> | Power<\/td> | Supply voltage; 1.65V to 3.6V; bypass with 0.1uF ceramic capacitor to GND<\/td><\/tr><\/tbody><\/table>","application_scenarios":"
|