{"id":9378,"date":"2026-07-03T06:18:02","date_gmt":"2026-07-03T06:18:02","guid":{"rendered":"https:\/\/materialparts.com\/mpc860srvr50d4r2\/"},"modified":"2026-07-03T07:37:42","modified_gmt":"2026-07-03T07:37:42","slug":"mpc860srvr50d4r2","status":"publish","type":"post","link":"https:\/\/materialparts.com\/ar\/mpc860srvr50d4r2\/","title":{"rendered":"MPC860SRVR50D4R2"},"content":{"rendered":"<h2>\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n<p>The MPC860SRVR50D4R2 is a PowerQUICC I communications processor from NXP Semiconductors (formerly Freescale). It integrates a 32-bit Power Architecture core running at 50MHz with a Communications Processor Module (CPM) containing 4 SCCs, 2 SMCs, SPI, and I2C. The MPC860SR variant supports ATM over UTOPIA in addition to 10\/100 Ethernet. Packaged in a 357-pin TBGA, this device is now obsolete but was widely deployed in networking and communications equipment.<\/p>\n<h2>\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n<table>\n<tr>\n<td>Core Architecture<\/td>\n<td>Power Architecture (MPC8xx)<\/td>\n<\/tr>\n<tr>\n<td>Core Frequency<\/td>\n<td>50 MHz<\/td>\n<\/tr>\n<tr>\n<td>Instruction Cache<\/td>\n<td>4 KB<\/td>\n<\/tr>\n<tr>\n<td>Data Cache<\/td>\n<td>4 KB<\/td>\n<\/tr>\n<tr>\n<td>On-Chip SRAM<\/td>\n<td>8 KB dual-port<\/td>\n<\/tr>\n<tr>\n<td>SCCs<\/td>\n<td>4<\/td>\n<\/tr>\n<tr>\n<td>SMCs<\/td>\n<td>2<\/td>\n<\/tr>\n<tr>\n<td>\u0625\u064a\u062b\u0631\u0646\u062a<\/td>\n<td>10\/100 Mbps (MII)<\/td>\n<\/tr>\n<tr>\n<td>ATM<\/td>\n<td>Yes (UTOPIA)<\/td>\n<\/tr>\n<tr>\n<td>SPI<\/td>\n<td>1<\/td>\n<\/tr>\n<tr>\n<td>I2C<\/td>\n<td>1<\/td>\n<\/tr>\n<tr>\n<td>Memory Controller<\/td>\n<td>8 banks (up to 32-bit data bus)<\/td>\n<\/tr>\n<tr>\n<td>Core Voltage<\/td>\n<td>2.5V<\/td>\n<\/tr>\n<tr>\n<td>I\/O Voltage<\/td>\n<td>3.3V<\/td>\n<\/tr>\n<tr>\n<td>\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\n<td>357-pin TBGA (25&#215;25 mm)<\/td>\n<\/tr>\n<tr>\n<td>\u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n<td>0C to +95C (Extended)<\/td>\n<\/tr>\n<tr>\n<td>\u062d\u0627\u0644\u0629 \u0627\u0644\u062c\u0632\u0621<\/td>\n<td>Obsolete<\/td>\n<\/tr>\n<\/table>\n<h2>\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n<ul>\n<li>32-bit Power Architecture core with MMU and caches<\/li>\n<li>Communications Processor Module (CPM) offloads protocol processing<\/li>\n<li>4 SCCs supporting Ethernet, HDLC, UART, transparent modes<\/li>\n<li>10\/100 Ethernet MII interface<\/li>\n<li>ATM support via UTOPIA interface (MPC860SR variant)<\/li>\n<li>PCMCIA socket controller (2 sockets)<\/li>\n<li>8-bank memory controller for DRAM, SRAM, EPROM, Flash<\/li>\n<\/ul>\n<h2>\u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n<ul>\n<li>Router and switch control plane processor<\/li>\n<li>T1\/E1 channelized communication controllers<\/li>\n<li>ATM edge switches and concentrators<\/li>\n<li>Industrial protocol gateways<\/li>\n<li>Telecom access equipment<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"<p>Product Overview The MPC860SRVR50D4R2 is a PowerQUICC I communications processor from NXP Semiconductors (formerly Freescale). It integrates a 32-bit Power Architecture core running at 50MHz with a Communications Processor Module (CPM) containing 4 SCCs, 2 SMCs, SPI, and I2C. The MPC860SR variant supports ATM over UTOPIA in addition to 10\/100 Ethernet. Packaged in a 357-pin [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,51],"tags":[524],"chip_brand":[168],"class_list":["post-9378","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-optocouplers-photocouplers","tag-mpc860srvr50d4r2","chip_brand-nxp"],"acf":{"brief_explanation":"PowerQUICC I MPC860SR, 50MHz Power Architecture, 4 SCCs, ATM UTOPIA, 10\/100 Ethernet, 357-TBGA, obsolete","date_code":"","package_case":"357-pin TBGA (25x25x1.82 mm)","in_stock":15590,"datasheet":"https:\/\/www.nxp.com\/docs\/en\/data-sheet\/MPC860EC.pdf","price":"$35.00 @ surplus","product_introduction":"The MPC860SRVR50D4R2 is a PowerQUICC I communications processor from NXP Semiconductors, integrating a 50MHz 32-bit Power Architecture core with a Communications Processor Module (CPM). The MPC860SR variant adds ATM UTOPIA support alongside 10\/100 Ethernet, making it suitable for multi-protocol networking equipment. With 4 SCCs, 2 SMCs, SPI, and I2C, the CPM offloads serial communication processing from the core, enabling efficient data plane operation. This device is now obsolete but was extensively used in telecom and networking infrastructure.","working_principle":"The MPC860SRVR50D4R2 uses a dual-processor architecture: the main Power Architecture core handles the control plane (OS, routing protocols, management), while the Communications Processor Module (CPM) with its own RISC core handles the data plane (serial I\/O, protocol processing). The CPM executes microcode in 8 KB dual-port SRAM, managing 4 SCCs that can independently handle Ethernet, HDLC, UART, or transparent mode protocols. For ATM, the UTOPIA interface connects to external PHY devices, with the CPM performing cell segmentation and reassembly (SAR). The 8-bank memory controller supports glueless interface to DRAM, SRAM, EPROM, and Flash. The core's MMU provides virtual memory support for embedded Linux or VxWorks operating systems. The PCMCIA controller supports two sockets for expansion cards.","pin_description":"<table>\n<tr><th>Pin Group<\/th><th>Name<\/th><th>Type<\/th><th>Function<\/th><\/tr>\n<tr><td>Core Power<\/td><td>VDDH, VDDL<\/td><td>Power<\/td><td>I\/O power (3.3V), Core power (2.5V)<\/td><\/tr>\n<tr><td>Address\/Data<\/td><td>A[0:31], D[0:31]<\/td><td>Bidirectional<\/td><td>32-bit address and data bus<\/td><\/tr>\n<tr><td>Ethernet<\/td><td>TXD[0:3], RXD[0:3], TX_CLK, RX_CLK<\/td><td>MII<\/td><td>MII interface to Ethernet PHY<\/td><\/tr>\n<tr><td>ATM<\/td><td>UTOPIA data and control<\/td><td>UTOPIA<\/td><td>ATM UTOPIA Level-1 master interface<\/td><\/tr>\n<tr><td>Serial<\/td><td>SCC1-4, SMC1-2, SPI, I2C<\/td><td>Serial<\/td><td>Multi-protocol serial communication pins<\/td><\/tr>\n<tr><td>Memory<\/td><td>CS[0:7], RAS, CAS, WE, OE<\/td><td>Control<\/td><td>8-bank memory controller interface<\/td><\/tr>\n<tr><td>JTAG<\/td><td>TCK, TMS, TDI, TDO, TRST<\/td><td>JTAG<\/td><td>Debug and boundary scan<\/td><\/tr>\n<\/table>","application_scenarios":"<table>\n<tr><th>Application<\/th><th>Circuit Role<\/th><th>Key Requirement<\/th><\/tr>\n<tr><td>Router Control Plane<\/td><td>Protocol processing CPU<\/td><td>50MHz Power Arch, 4 SCC, Ethernet<\/td><\/tr>\n<tr><td>T1\/E1 Channelized<\/td><td>HDLC\/multi-channel controller<\/td><td>4 SCC, time-slot assigner<\/td><\/tr>\n<tr><td>ATM Edge Switch<\/td><td>ATM SAR and cell processing<\/td><td>UTOPIA, 4 SCC, ATM microcode<\/td><\/tr>\n<tr><td>Industrial Gateway<\/td><td>Protocol converter<\/td><td>Multi-serial, Ethernet, SPI, I2C<\/td><\/tr>\n<tr><td>Access Concentrator<\/td><td>DSLAM controller<\/td><td>ATM, Ethernet, 50MHz core<\/td><\/tr>\n<\/table>","alternative_models":"<table>\n<tr><th>Model<\/th><th>Manufacturer<\/th><th>Key Difference<\/th><\/tr>\n<tr><td>MPC860TVR50D4<\/td><td>NXP<\/td><td>MPC860T variant, ATM support, PQFP package<\/td><\/tr>\n<tr><td>MPC855TVR50D4<\/td><td>NXP<\/td><td>MPC855T, reduced SCC count<\/td><\/tr>\n<tr><td>MPC8270VR133D4<\/td><td>NXP<\/td><td>PowerQUICC II, 133MHz, 603e core<\/td><\/tr>\n<tr><td>MPC8313ERVRAGDA<\/td><td>NXP<\/td><td>PowerQUICC II Pro, e300 core, 333MHz<\/td><\/tr>\n<tr><td>P1010NSN5FNJ<\/td><td>NXP<\/td><td>QorIQ P1, e500 core, 400MHz, newer<\/td><\/tr>\n<\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/9378","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/comments?post=9378"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/9378\/revisions"}],"predecessor-version":[{"id":9407,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/9378\/revisions\/9407"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/media?parent=9378"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/categories?post=9378"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/tags?post=9378"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=9378"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}