{"id":8936,"date":"2026-07-01T02:47:26","date_gmt":"2026-07-01T02:47:26","guid":{"rendered":"https:\/\/materialparts.com\/sn74lvc74adr-2\/"},"modified":"2026-07-01T02:47:26","modified_gmt":"2026-07-01T02:47:26","slug":"sn74lvc74adr-2","status":"publish","type":"post","link":"https:\/\/materialparts.com\/ar\/sn74lvc74adr-2\/","title":{"rendered":"SN74LVC74ADR"},"content":{"rendered":"

\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n

The SN74LVC74ADR is a Texas Instruments dual D-type positive-edge-triggered flip-flop with preset, clear, and 3-state outputs. 1.65-3.6V supply, 5.5V tolerant inputs. Packaged in SOIC-14, -40C to +125C.<\/p>\n

\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n\n\n\n\n\n\n\n
\u0627\u0644\u0642\u0646\u0648\u0627\u062a<\/td>\n2 (dual)<\/td>\n<\/tr>\n
\u0627\u0644\u0646\u0648\u0639<\/td>\nD flip-flop, edge-triggered<\/td>\n<\/tr>\n
Supply<\/td>\n1.65 V to 3.6 V<\/td>\n<\/tr>\n
fmax<\/td>\n>200 MHz at 3.3V<\/td>\n<\/tr>\n
Input Tolerance<\/td>\n5.5 V<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\nSOIC-14<\/td>\n<\/tr>\n<\/table>\n

\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n
    \n
  • Dual D flip-flop with preset\/clear<\/li>\n
  • Positive-edge-triggered clock<\/li>\n
  • 1.65V to 3.6V supply<\/li>\n
  • 5.5V tolerant inputs<\/li>\n
  • >200MHz max clock frequency<\/li>\n
  • Complementary Q and Q-bar outputs<\/li>\n
  • Ioff partial-power-down support<\/li>\n<\/ul>\n

    \u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n
      \n
    • Clock division and sync<\/li>\n
    • Data latch and pipeline<\/li>\n
    • Control state machine<\/li>\n
    • Level translation<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LVC74ADR is a Texas Instruments dual D-type positive-edge-triggered flip-flop with preset, clear, and 3-state outputs. 1.65-3.6V supply, 5.5V tolerant inputs. Packaged in SOIC-14, -40C to +125C. Key Specifications Channels 2 (dual) Type D flip-flop, edge-triggered Supply 1.65 V to 3.6 V fmax >200 MHz at 3.3V Input Tolerance 5.5 V Package SOIC-14 […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-8936","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual D FF, preset\/clear, 5.5V input, SOIC-14","date_code":"","package_case":"14-Pin SOIC (8.65 x 3.9 x 1.5 mm)","in_stock":8500,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74lvc74a.pdf","price":"$0.350 @ 1ku","product_introduction":"The SN74LVC74ADR is a Texas Instruments dual D-type positive-edge-triggered flip-flop with asynchronous preset (PRE) and clear (CLR) inputs in a 14-pin SOIC package. Each flip-flop captures the D input on the rising edge of the clock (CLK) and presents it at the Q output, with the complementary Q-bar output always opposite. The asynchronous PRE (active low) sets Q high regardless of clock, and CLR (active low) resets Q low. Both PRE and CLR override the clocked operation, providing flexible initialization and fault handling. The 1.65V to 3.6V supply range supports 1.8V, 2.5V, and 3.3V logic systems. The 5.5V input tolerance allows direct interfacing with 5V logic devices, enabling 5V-to-3.3V level translation. The >200MHz maximum clock frequency at 3.3V supports high-speed clock division and data pipeline applications. The Ioff feature disables the output circuitry during partial power-down, preventing backflow current. The LVC architecture provides low static power consumption with high output drive (24mA at 3.3V). Packaged in SOIC-14 rated for -40C to +125C.","working_principle":"The SN74LVC74A contains two independent D flip-flops, each implemented as a master-slave latch. On the rising edge of CLK, the master latch opens and captures the D input value while the slave latch holds the previous Q output. After the clock transition, the master closes and the slave opens, transferring the new value to the Q output. This edge-triggered behavior prevents transparent latching that could cause race conditions. The asynchronous PRE input asserts Q=1 and Q-bar=0 by directly setting the slave latch, overriding the clocked D input. Similarly, CLR asserts Q=0 and Q-bar=1 by directly resetting the slave latch. If both PRE and CLR are asserted simultaneously, both Q and Q-bar go high (invalid state), which resolves when either preset or clear is released. The input clamp diodes protect against overshoot and allow 5.5V inputs when VCC is 3.3V. The output stage uses a push-pull CMOS driver sized for 24mA symmetric drive.","pin_description":"
      Pin<\/th>Mnemonic<\/th>Description<\/th><\/tr>
      1<\/td>1CLR<\/td>Clear 1 (active low)<\/td><\/tr>
      2<\/td>1D<\/td>Data input 1<\/td><\/tr>
      3<\/td>1CLK<\/td>Clock 1 (rising edge)<\/td><\/tr>
      4<\/td>1PRE<\/td>Preset 1 (active low)<\/td><\/tr>
      5<\/td>1Q<\/td>Output 1<\/td><\/tr>
      6<\/td>1Q-bar<\/td>Complementary output 1<\/td><\/tr>
      7<\/td>GND<\/td>Ground<\/td><\/tr>
      8<\/td>2Q-bar<\/td>Complementary output 2<\/td><\/tr>
      9<\/td>2Q<\/td>Output 2<\/td><\/tr>
      10<\/td>2PRE<\/td>Preset 2 (active low)<\/td><\/tr>
      11<\/td>2CLK<\/td>Clock 2 (rising edge)<\/td><\/tr>
      12<\/td>2D<\/td>Data input 2<\/td><\/tr>
      13<\/td>2CLR<\/td>Clear 2 (active low)<\/td><\/tr>
      14<\/td>VCC<\/td>Supply (1.65-3.6V)<\/td><\/tr><\/table>","application_scenarios":"
      • Clock division by 2 with D tied to Q-bar for toggle flip-flop operation at >200MHz<\/li>\n
      • Data pipeline stage with edge-triggered capture and preset\/clear for initialization<\/li>\n
      • Control state machine element with asynchronous clear for fault reset<\/li>\n
      • 5V-to-3.3V level translation with 5.5V tolerant inputs and clocked data capture<\/li><\/ul>","alternative_models":"
        Model<\/th>Manufacturer<\/th>Key Difference<\/th><\/tr>
        SN74LVC74APWR<\/td>TI<\/td>TSSOP-14 package<\/td><\/tr>
        SN74AUC74<\/td>TI<\/td>0.8V, ultra-low voltage<\/td><\/tr>
        74LVC74APW<\/td>Nexperia<\/td>Similar dual D FF<\/td><\/tr>
        NC7SV74<\/td>onsemi<\/td>Single D FF, tiny<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/8936","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/comments?post=8936"}],"version-history":[{"count":0,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/8936\/revisions"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/media?parent=8936"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/categories?post=8936"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/tags?post=8936"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=8936"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}