{"id":8782,"date":"2026-06-30T08:30:27","date_gmt":"2026-06-30T08:30:27","guid":{"rendered":"https:\/\/materialparts.com\/sn74lvc74adr\/"},"modified":"2026-06-30T08:30:27","modified_gmt":"2026-06-30T08:30:27","slug":"sn74lvc74adr","status":"publish","type":"post","link":"https:\/\/materialparts.com\/ar\/sn74lvc74adr\/","title":{"rendered":"SN74LVC74ADR"},"content":{"rendered":"

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The SN74LVC74ADR is a Texas Instruments dual positive-edge-triggered D-type flip-flop with preset and clear in a 14-pin SOIC package. It operates from 1.65V to 3.6V with 5.5V-tolerant inputs, 5.2ns max propagation delay at 3.3V, and latch-up exceeding 250mA. Rated for -40C to +125C.<\/p>\n

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\u0627\u0644\u0648\u0638\u064a\u0641\u0629<\/td>\nDual D flip-flop<\/td>\n<\/tr>\n
Trigger<\/td>\nPositive-edge<\/td>\n<\/tr>\n
VCC Range<\/td>\n1.65 V to 3.6 V<\/td>\n<\/tr>\n
tpd (max)<\/td>\n5.2 ns at 3.3 V<\/td>\n<\/tr>\n
\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/td>\nPreset, Clear<\/td>\n<\/tr>\n
fmax<\/td>\n~150 MHz<\/td>\n<\/tr>\n<\/table>\n

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    \n
  • Dual D-type positive-edge-triggered flip-flops<\/li>\n
  • Asynchronous preset and clear<\/li>\n
  • 1.65V to 3.6V operation<\/li>\n
  • 5.5V tolerant inputs<\/li>\n
  • 5.2ns max propagation delay<\/li>\n
  • ESD: 2000V HBM, 1000V CDM<\/li>\n
  • SOIC-14 package<\/li>\n<\/ul>\n

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      \n
    • Clock division and synchronization<\/li>\n
    • State machine and control logic<\/li>\n
    • Data storage and transfer<\/li>\n
    • Frequency synthesis<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LVC74ADR is a Texas Instruments dual positive-edge-triggered D-type flip-flop with preset and clear in a 14-pin SOIC package. It operates from 1.65V to 3.6V with 5.5V-tolerant inputs, 5.2ns max propagation delay at 3.3V, and latch-up exceeding 250mA. Rated for -40C to +125C. Key Specifications Function Dual D flip-flop Trigger Positive-edge VCC Range […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-8782","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual D flip-flop, pos-edge, preset\/clear, 1.65-3.6V, 5.2ns, SOIC-14","date_code":"","package_case":"14-Pin SOIC (8.65 x 3.91 x 1.27 mm)","in_stock":11200,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74lvc74a.pdf","price":"$0.35 @ 1ku","product_introduction":"The SN74LVC74ADR is a Texas Instruments dual positive-edge-triggered D-type flip-flop with individual asynchronous preset (PRE, active low) and clear (CLR, active low) inputs. Each flip-flop stores one bit of data, with the Q output following the D input on the rising edge of the clock (CLK). The preset and clear inputs override the clock and data inputs, directly setting or resetting the outputs. The device operates from 1.65V to 3.6V VCC with inputs accepting voltages to 5.5V for mixed-voltage systems. The 5.2ns maximum propagation delay at 3.3V enables operation up to approximately 150 MHz. ESD protection exceeds 2000V HBM and 1000V charged-device model. Latch-up performance exceeds 250mA per JESD 17. Packaged in 14-pin SOIC rated for -40C to +125C.","working_principle":"Each flip-flop in the SN74LVC74A consists of a master-slave latch configuration optimized for positive-edge triggering. On the rising edge of CLK, the D input is sampled and transferred to the Q output. The asynchronous preset (PRE) and clear (CLR) inputs use internal gating logic to override the clocked operation: a low on PRE sets Q high regardless of CLK and D, while a low on CLR resets Q low. Simultaneous low on both PRE and CLR is normally prohibited as both Q and Q-bar will go high. The CMOS implementation uses transmission gates and inverters for the master and slave latches, providing low static power consumption and rail-to-rail output swing.","pin_description":"
      Pin<\/th>Mnemonic<\/th>Description<\/th><\/tr>
      1<\/td>1CLR<\/td>Clear 1 (active low)<\/td><\/tr>
      2<\/td>1D<\/td>Data input 1<\/td><\/tr>
      3<\/td>1CLK<\/td>Clock input 1 (rising edge)<\/td><\/tr>
      4<\/td>1PRE<\/td>Preset 1 (active low)<\/td><\/tr>
      5,6<\/td>1Q,1Q<\/td>Output 1, complement<\/td><\/tr>
      7<\/td>GND<\/td>Ground<\/td><\/tr>
      8-13<\/td>2Q-2CLR<\/td>Flip-flop 2 (mirror)<\/td><\/tr>
      14<\/td>VCC<\/td>Supply<\/td><\/tr><\/table>","application_scenarios":"
      • Clock division by 2 with D tied to Q-bar for frequency halving<\/li>\n
      • State machine control logic with preset\/clear for initialization<\/li>\n
      • Data synchronization from asynchronous domain to clocked domain<\/li>\n
      • 5V-to-3.3V level-sensitive storage with 5.5V tolerant inputs<\/li><\/ul>","alternative_models":"
        Model<\/th>Manufacturer<\/th>Key Difference<\/th><\/tr>
        SN74LVC74APW<\/td>TI<\/td>TSSOP-14 package<\/td><\/tr>
        74LVC74APW<\/td>NXP<\/td>Pin-compatible NXP<\/td><\/tr>
        SN74AUC74<\/td>TI<\/td>Ultra-low voltage (0.8V)<\/td><\/tr>
        SN74LVC2G74<\/td>TI<\/td>Single flip-flop, tiny<\/td><\/tr><\/table>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/8782","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/comments?post=8782"}],"version-history":[{"count":0,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/8782\/revisions"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/media?parent=8782"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/categories?post=8782"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/tags?post=8782"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=8782"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}