{"id":7993,"date":"2026-06-28T06:32:25","date_gmt":"2026-06-28T06:32:25","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls76an\/"},"modified":"2026-06-28T11:44:26","modified_gmt":"2026-06-28T11:44:26","slug":"sn74ls76an","status":"publish","type":"post","link":"https:\/\/materialparts.com\/ar\/sn74ls76an\/","title":{"rendered":"SN74LS76AN"},"content":{"rendered":"

\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n

The SN74LS76AN from Texas Instruments contains two independent J-K flip-flops with complementary outputs, preset and clear \u2014 more versatile than the D flip-flop 7474 thanks to J-K logic in a 16-pin PDIP package.<\/p>\n

\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n
Number of Flip-Flops<\/td>\n2 (dual, independent)<\/td>\n<\/tr>\n
\u0639\u0627\u0626\u0644\u0629 \u0627\u0644\u0645\u0646\u0637\u0642<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Trigger Type<\/td>\nNegative-edge (falling edge of CLK)<\/td>\n<\/tr>\n
\u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u062f \u0627\u0644\u0623\u0642\u0635\u0649 \u0644\u062a\u0631\u062f\u062f \u0627\u0644\u0633\u0627\u0639\u0629<\/td>\n30MHz typical<\/td>\n<\/tr>\n
J, K Inputs<\/td>\nLevel-triggered (set before clock edge)<\/td>\n<\/tr>\n
Preset (PRE)<\/td>\nActive-LOW (asynchronous, sets Q=1)<\/td>\n<\/tr>\n
Clear (CLR)<\/td>\nActive-LOW (asynchronous, sets Q=0)<\/td>\n<\/tr>\n
\u062a\u0623\u062e\u064a\u0631 \u0627\u0644\u0627\u0646\u062a\u0634\u0627\u0631<\/td>\n15-20ns (CLK to Q)<\/td>\n<\/tr>\n
\u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n
    \n
  • Dual J-K negative-edge-triggered flip-flops<\/li>\n
  • J=0,K=0: hold; J=1,K=0: set; J=0,K=1: reset; J=1,K=1: toggle<\/li>\n
  • Asynchronous preset and clear (active-LOW)<\/li>\n
  • Complementary outputs (Q and NOT-Q)<\/li>\n
  • 30MHz clock frequency<\/li>\n<\/ul>\n

    \u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n
      \n
    • Toggle flip-flop \/ frequency divider<\/li>\n
    • Data register<\/li>\n
    • Counter building block<\/li>\n
    • Control logic<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS76AN from Texas Instruments contains two independent J-K flip-flops with complementary outputs, preset and clear \u2014 more versatile than the D flip-flop 7474 thanks to J-K logic in a 16-pin PDIP package. Key Specifications Number of Flip-Flops 2 (dual, independent) Logic Family LS (Low-power Schottky) Trigger Type Negative-edge (falling edge of CLK) […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7993","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual J-K flip-flop, negative-edge, preset\/clear, LS TTL, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":4000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls76a.pdf","price":"$0.50 @ 1ku","product_introduction":"The SN74LS76AN from Texas Instruments contains two independent J-K negative-edge-triggered flip-flops with direct preset (PRE, active-LOW) and clear (CLR, active-LOW). The J-K flip-flop is more versatile than the D flip-flop because it has four operating modes: hold (J=0,K=0), set (J=1,K=0), reset (J=0,K=1), and toggle (J=1,K=1). The toggle mode makes the 7476 ideal for frequency division: connecting J and K both HIGH causes Q to toggle on each falling clock edge, dividing the clock by 2. The 7476 triggers on the negative (falling) edge of the clock, unlike the 7474 which triggers on the positive (rising) edge. The asynchronous PRE and CLR override the clock: PRE=LOW forces Q=1; CLR=LOW forces Q=0. Both PRE and CLR must be HIGH for normal clocked operation. The 7476 is used in counter designs, control sequencers, and wherever J-K functionality is needed. The A suffix denotes the improved LS version; the N suffix denotes the PDIP-16 through-hole package.","working_principle":"Each J-K flip-flop in the SN74LS76AN captures the J and K input states on the falling edge of CLK and updates the Q output accordingly. Truth table (on falling CLK edge): J=0,K=0 \u2192 Q holds; J=1,K=0 \u2192 Q=1 (set); J=0,K=1 \u2192 Q=0 (reset); J=1,K=1 \u2192 Q toggles. The J and K inputs must be stable before the falling clock edge (setup time ~10ns). Asynchronous inputs override: PRE=LOW forces Q=1 regardless of CLK, J, K; CLR=LOW forces Q=0. Both PRE and CLR active simultaneously (both LOW) is invalid (Q and NOT-Q both HIGH). For toggle mode: J=K=1; each falling clock edge toggles Q; Q frequency = CLK\/2. For frequency division by 4: cascade two 7476 flip-flops in toggle mode; Q1 \u2192 CLK2; Q2 frequency = CLK\/4. For a 2-bit binary counter: two 7476s in toggle mode, Q1 drives CLK2; Q1,Q0 count 00\u219201\u219210\u219211\u219200. For a controlled set\/reset: J and K control what happens on the next clock edge; J=1 sets, K=1 resets, both=1 toggles, both=0 holds.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1CLR<\/td>Input<\/td>Flip-flop 1 clear (active LOW)<\/td><\/tr>\n
      2<\/td>1Q<\/td>Output<\/td>Flip-flop 1 Q output<\/td><\/tr>\n
      3<\/td>1NOT-Q<\/td>Output<\/td>Flip-flop 1 complementary output<\/td><\/tr>\n
      4<\/td>1J<\/td>Input<\/td>Flip-flop 1 J input<\/td><\/tr>\n
      5<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n
      6<\/td>1CLK<\/td>Input<\/td>Flip-flop 1 clock (negative edge)<\/td><\/tr>\n
      7<\/td>1K<\/td>Input<\/td>Flip-flop 1 K input<\/td><\/tr>\n
      8<\/td>1PRE<\/td>Input<\/td>Flip-flop 1 preset (active LOW)<\/td><\/tr>\n
      9<\/td>2PRE<\/td>Input<\/td>Flip-flop 2 preset (active LOW)<\/td><\/tr>\n
      10<\/td>2K<\/td>Input<\/td>Flip-flop 2 K input<\/td><\/tr>\n
      11<\/td>2CLK<\/td>Input<\/td>Flip-flop 2 clock (negative edge)<\/td><\/tr>\n
      12<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      13<\/td>2J<\/td>Input<\/td>Flip-flop 2 J input<\/td><\/tr>\n
      14<\/td>2NOT-Q<\/td>Output<\/td>Flip-flop 2 complementary output<\/td><\/tr>\n
      15<\/td>2Q<\/td>Output<\/td>Flip-flop 2 Q output<\/td><\/tr>\n
      16<\/td>2CLR<\/td>Input<\/td>Flip-flop 2 clear (active LOW)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Toggle \/ \u00f72:<\/strong> J=K=1 (tied HIGH); clock on CLK; Q toggles each falling edge; Q = CLK\/2<\/li>\n
      • 2-Bit Ripple Counter:<\/strong> FF1: J=K=1, clock=input; Q1\u2192CLK2; FF2: J=K=1; Q2,Q1 = 2-bit count (00\u219201\u219210\u219211)<\/li>\n
      • Controlled Latch:<\/strong> J=data, K=NOT-data; on falling CLK, Q captures data value (equivalent to D flip-flop with inverter)<\/li>\n
      • Gated Oscillator:<\/strong> J=enable, K=enable; enable=1 \u2192 toggle; enable=0 \u2192 hold; gated clock output on Q<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS76N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS76D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC76D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC76N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT76D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT76N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n<\/table>\n

        The 7476 is a Dual J-K Flip-Flop with Clear and Preset. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7993","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/comments?post=7993"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7993\/revisions"}],"predecessor-version":[{"id":8145,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7993\/revisions\/8145"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/media?parent=7993"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/categories?post=7993"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/tags?post=7993"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=7993"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}