{"id":7982,"date":"2026-06-28T06:25:42","date_gmt":"2026-06-28T06:25:42","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls74an-3\/"},"modified":"2026-06-28T11:44:44","modified_gmt":"2026-06-28T11:44:44","slug":"sn74ls74an-3","status":"publish","type":"post","link":"https:\/\/materialparts.com\/ar\/sn74ls74an-3\/","title":{"rendered":"SN74LS74AN"},"content":{"rendered":"

\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n

The SN74LS74AN from Texas Instruments contains two independent D-type positive-edge-triggered flip-flops with complementary outputs, direct preset and clear \u2014 the TTL counterpart of the CD4013 for 5V systems in a 14-pin PDIP package.<\/p>\n

\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n\n\n\n\n\n\n\n\n\n\n\n\n
Number of Flip-Flops<\/td>\n2 (dual, independent)<\/td>\n<\/tr>\n
\u0639\u0627\u0626\u0644\u0629 \u0627\u0644\u0645\u0646\u0637\u0642<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Trigger Type<\/td>\nPositive-edge (rising edge of CLK)<\/td>\n<\/tr>\n
\u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u062f \u0627\u0644\u0623\u0642\u0635\u0649 \u0644\u062a\u0631\u062f\u062f \u0627\u0644\u0633\u0627\u0639\u0629<\/td>\n25MHz typical<\/td>\n<\/tr>\n
Preset (PRE)<\/td>\nActive-LOW (asynchronous, sets Q=1)<\/td>\n<\/tr>\n
Clear (CLR)<\/td>\nActive-LOW (asynchronous, sets Q=0)<\/td>\n<\/tr>\n
Setup Time<\/td>\n10ns typical<\/td>\n<\/tr>\n
\u062a\u0623\u062e\u064a\u0631 \u0627\u0644\u0627\u0646\u062a\u0634\u0627\u0631<\/td>\n13\u201325ns (CLK to Q)<\/td>\n<\/tr>\n
\u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\nPDIP-14 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n
    \n
  • Dual D-type flip-flops, positive-edge triggered<\/li>\n
  • Asynchronous preset and clear (active-LOW)<\/li>\n
  • Complementary outputs (Q and NOT-Q)<\/li>\n
  • 25MHz clock frequency<\/li>\n
  • Industry-standard 7474 pinout<\/li>\n<\/ul>\n

    \u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n
      \n
    • Data register \/ latch<\/li>\n
    • Frequency divider (toggle mode)<\/li>\n
    • Switch debounce<\/li>\n
    • Sync logic in digital systems<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS74AN from Texas Instruments contains two independent D-type positive-edge-triggered flip-flops with complementary outputs, direct preset and clear \u2014 the TTL counterpart of the CD4013 for 5V systems in a 14-pin PDIP package. Key Specifications Number of Flip-Flops 2 (dual, independent) Logic Family LS (Low-power Schottky) Trigger Type Positive-edge (rising edge of CLK) […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7982","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual D flip-flop, LS TTL, preset\/clear, 25MHz, PDIP-14","date_code":"","package_case":"PDIP-14 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":6000,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls74a.pdf","price":"$0.40 @ 1ku","product_introduction":"The SN74LS74AN from Texas Instruments contains two independent D-type positive-edge-triggered flip-flops with direct preset (PRE, active-LOW) and clear (CLR, active-LOW). On each rising edge of the clock, the D input is captured and appears at the Q output. The asynchronous preset (PRE=LOW) forces Q=1 regardless of CLK and D; the asynchronous clear (CLR=LOW) forces Q=0. The 7474 is the TTL counterpart of the CMOS CD4013, with active-LOW (rather than active-HIGH) preset and clear. This is the most commonly used flip-flop in TTL systems for data registers, frequency dividers, and synchronization logic. In toggle mode (NOT-Q connected to D), each flip-flop divides the clock frequency by 2. Two flip-flops in one package can divide by 4, or store 2 bits of data. The 25MHz clock frequency supports medium-speed digital systems. The A suffix denotes the improved LS version; the N suffix denotes the PDIP-14 through-hole package.","working_principle":"Each D flip-flop in the SN74LS74AN captures the D input on the rising edge of CLK and holds it at Q until the next rising edge. Truth table: CLK rising edge with D=0 \u2192 Q=0; D=1 \u2192 Q=1. When CLK is not rising, Q holds regardless of D. The asynchronous inputs override: PRE=LOW forces Q=1; CLR=LOW forces Q=0. Both PRE and CLR are active-LOW (unlike CD4013's active-HIGH S and R). For normal operation, both PRE and CLR must be HIGH. If both PRE and CLR are simultaneously LOW, both Q and NOT-Q go HIGH (invalid); the final state after both are released is indeterminate. For toggle mode: NOT-Q \u2192 D; each rising clock edge toggles Q; Q frequency = CLK\/2. Two 7474 flip-flops cascade: Q1 \u2192 D2, NOT-Q1 \u2192 D1, shared clock = divide-by-4. For data storage: parallel data on D1 and D2; CLK rising edge captures both bits simultaneously. The 10ns setup time means D must be stable at least 10ns before the clock edge.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1CLR<\/td>Input<\/td>Flip-flop 1 clear (active LOW, sets Q=0)<\/td><\/tr>\n
      2<\/td>1D<\/td>Input<\/td>Flip-flop 1 data input<\/td><\/tr>\n
      3<\/td>1CLK<\/td>Input<\/td>Flip-flop 1 clock (rising edge)<\/td><\/tr>\n
      4<\/td>1PRE<\/td>Input<\/td>Flip-flop 1 preset (active LOW, sets Q=1)<\/td><\/tr>\n
      5<\/td>1Q<\/td>Output<\/td>Flip-flop 1 Q output<\/td><\/tr>\n
      6<\/td>1NOT-Q<\/td>Output<\/td>Flip-flop 1 complementary output<\/td><\/tr>\n
      7<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      8<\/td>2NOT-Q<\/td>Output<\/td>Flip-flop 2 complementary output<\/td><\/tr>\n
      9<\/td>2Q<\/td>Output<\/td>Flip-flop 2 Q output<\/td><\/tr>\n
      10<\/td>2PRE<\/td>Input<\/td>Flip-flop 2 preset (active LOW)<\/td><\/tr>\n
      11<\/td>2CLK<\/td>Input<\/td>Flip-flop 2 clock (rising edge)<\/td><\/tr>\n
      12<\/td>2D<\/td>Input<\/td>Flip-flop 2 data input<\/td><\/tr>\n
      13<\/td>2CLR<\/td>Input<\/td>Flip-flop 2 clear (active LOW)<\/td><\/tr>\n
      14<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Toggle \/ Divide-by-2:<\/strong> 1NOT-Q \u2192 1D; clock on 1CLK; 1Q = clock\/2; 2NOT-Q \u2192 2D; 1Q \u2192 2CLK; 2Q = clock\/4<\/li>\n
      • 2-Bit Register:<\/strong> Data on 1D and 2D; shared CLK rising edge captures both bits; PRE and CLR tied HIGH for normal operation<\/li>\n
      • Sync Logic:<\/strong> Asynchronous input \u2192 D1; system clock \u2192 CLK; Q1 = synchronized version of input; eliminates metastability<\/li>\n
      • One-Shot:<\/strong> D tied HIGH; trigger on CLR (LOW pulse); CLK free-running; one clock-wide pulse on Q after CLR released<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS74N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-14<\/td>5V TTL<\/td><\/tr>\n
        74LS74D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-14<\/td>5V TTL<\/td><\/tr>\n
        74HC74D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT74D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-14<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74AC74D<\/td>TI\/Nexperia<\/td>Advanced CMOS with 2-6V supply and higher output drive current (24mA vs 6mA for HC)<\/td>SOIC-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74AC74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of AC family for prototyping and repair<\/td>DIP-14<\/td>2-6V CMOS<\/td><\/tr>\n
        74LVC74D<\/td>TI\/Nexperia<\/td>Low-voltage CMOS for 1.65-3.6V modern logic with 24mA output drive and bus-hold inputs<\/td>SOIC-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n
        74LVC74N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of LVC family for prototyping and repair<\/td>DIP-14<\/td>1.65-3.6V CMOS<\/td><\/tr>\n<\/table>\n

        The 7474 is a Dual D-Type Positive-Edge-Triggered Flip-Flop. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7982","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/comments?post=7982"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7982\/revisions"}],"predecessor-version":[{"id":8154,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7982\/revisions\/8154"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/media?parent=7982"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/categories?post=7982"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/tags?post=7982"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=7982"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}