{"id":7963,"date":"2026-06-28T06:10:27","date_gmt":"2026-06-28T06:10:27","guid":{"rendered":"https:\/\/materialparts.com\/sn74ls112n\/"},"modified":"2026-06-28T11:45:11","modified_gmt":"2026-06-28T11:45:11","slug":"sn74ls112n","status":"publish","type":"post","link":"https:\/\/materialparts.com\/ar\/sn74ls112n\/","title":{"rendered":"SN74LS112N"},"content":{"rendered":"

\u0646\u0638\u0631\u0629 \u0639\u0627\u0645\u0629 \u0639\u0644\u0649 \u0627\u0644\u0645\u0646\u062a\u062c<\/h2>\n

The SN74LS112N from Texas Instruments is a dual negative-edge-triggered J-K flip-flop with preset and clear inputs, capable of toggle, latch, and shift register functions in a 16-pin PDIP package.<\/p>\n

\u0627\u0644\u0645\u0648\u0627\u0635\u0641\u0627\u062a \u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629<\/h2>\n\n\n\n\n\n\n\n\n\n\n
Number of Flip-Flops<\/td>\n2 (dual, independent)<\/td>\n<\/tr>\n
\u0639\u0627\u0626\u0644\u0629 \u0627\u0644\u0645\u0646\u0637\u0642<\/td>\nLS (Low-power Schottky)<\/td>\n<\/tr>\n
Trigger Type<\/td>\nNegative-edge (falling edge of CLK)<\/td>\n<\/tr>\n
\u062c\u0647\u062f \u0627\u0644\u0625\u0645\u062f\u0627\u062f<\/td>\n4.75V to 5.25V<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u062f \u0627\u0644\u0623\u0642\u0635\u0649 \u0644\u062a\u0631\u062f\u062f \u0627\u0644\u0633\u0627\u0639\u0629<\/td>\n30MHz typical<\/td>\n<\/tr>\n
Preset (PRE)<\/td>\nActive LOW (asynchronous, sets Q=1)<\/td>\n<\/tr>\n
Clear (CLR)<\/td>\nActive LOW (asynchronous, sets Q=0)<\/td>\n<\/tr>\n
\u062f\u0631\u062c\u0629 \u062d\u0631\u0627\u0631\u0629 \u0627\u0644\u062a\u0634\u063a\u064a\u0644<\/td>\n0\u00b0C to +70\u00b0C<\/td>\n<\/tr>\n
\u0627\u0644\u062d\u0632\u0645\u0629<\/td>\nPDIP-16 (19.3 x 6.35mm)<\/td>\n<\/tr>\n<\/table>\n

\u0627\u0644\u0645\u064a\u0632\u0627\u062a<\/h2>\n
    \n
  • Dual J-K flip-flops, negative-edge triggered<\/li>\n
  • Asynchronous preset and clear<\/li>\n
  • J-K inputs: toggle mode (J=K=1), hold (J=K=0), set (J=1,K=0), reset (J=0,K=1)<\/li>\n
  • 30MHz maximum clock frequency<\/li>\n<\/ul>\n

    \u0627\u0644\u062a\u0637\u0628\u064a\u0642\u0627\u062a<\/h2>\n
      \n
    • Frequency divider (toggle mode)<\/li>\n
    • Shift register building block<\/li>\n
    • Counter building block<\/li>\n
    • Event latch<\/li>\n<\/ul>","protected":false},"excerpt":{"rendered":"

      Product Overview The SN74LS112N from Texas Instruments is a dual negative-edge-triggered J-K flip-flop with preset and clear inputs, capable of toggle, latch, and shift register functions in a 16-pin PDIP package. Key Specifications Number of Flip-Flops 2 (dual, independent) Logic Family LS (Low-power Schottky) Trigger Type Negative-edge (falling edge of CLK) Supply Voltage 4.75V to […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[13,20],"tags":[],"chip_brand":[138],"class_list":["post-7963","post","type-post","status-publish","format-standard","hentry","category-integrated-circuits-ics","category-interface-ics","chip_brand-ti"],"acf":{"brief_explanation":"Dual J-K flip-flop, negative-edge, preset\/clear, PDIP-16","date_code":"","package_case":"PDIP-16 (19.3 x 6.35 x 4.57mm, 2.54mm pitch, through-hole)","in_stock":3500,"datasheet":"https:\/\/www.ti.com\/lit\/ds\/symlink\/sn74ls112a.pdf","price":"$0.50 @ 1ku","product_introduction":"The SN74LS112N from Texas Instruments contains two independent negative-edge-triggered J-K flip-flops with asynchronous preset (PRE, active LOW) and clear (CLR, active LOW) inputs. The J-K flip-flop is the most versatile flip-flop type: it can toggle (J=K=1), hold its state (J=K=0), set (J=1, K=0), or reset (J=0, K=1). In toggle mode, the output divides the clock frequency by 2, making it ideal for frequency dividers and binary counter chains. The negative-edge trigger means the output changes on the falling edge of the clock, which is important for cascaded counters where ripple delays must be accommodated. The asynchronous PRE and CLR inputs override the clocked operation: PRE forces Q=1 regardless of J, K, or CLK; CLR forces Q=0. Both PRE and CLR should be HIGH for normal clocked operation. The N suffix denotes the PDIP-16 through-hole package.","working_principle":"Each J-K flip-flop in the SN74LS112N operates on the falling edge of the clock. The J and K inputs are sampled just before the falling edge, and the output transitions according to: J=0,K=0: Q holds (no change); J=0,K=1: Q goes to 0 (reset); J=1,K=0: Q goes to 1 (set); J=1,K=1: Q toggles (inverts). The setup time requirement means J and K must be stable for at least 20ns before the falling clock edge. The hold time requirement (typically 0ns for LS) means J and K must remain stable for 0ns after the falling edge. In toggle mode (J=K=1), each falling clock edge inverts Q, so the output completes one full cycle for every two clock cycles \u2014 a divide-by-2 function. Cascading two toggle flip-flops creates a divide-by-4; three creates divide-by-8, etc. The asynchronous PRE (preset) input forces Q=1 immediately when brought LOW, regardless of the clock. Similarly, CLR (clear) forces Q=0. If both PRE and CLR are LOW simultaneously, both Q and NOT-Q go HIGH (invalid state); the final state after both are released is indeterminate.","pin_description":"\n
      Pin<\/th>Name<\/th>Type<\/th>Description<\/th><\/tr>\n
      1<\/td>1CLK<\/td>Input<\/td>Flip-flop 1 clock (falling edge triggered)<\/td><\/tr>\n
      2<\/td>1K<\/td>Input<\/td>Flip-flop 1 K input<\/td><\/tr>\n
      3<\/td>1J<\/td>Input<\/td>Flip-flop 1 J input<\/td><\/tr>\n
      4<\/td>1PRE<\/td>Input<\/td>Flip-flop 1 preset (active LOW, sets Q=1)<\/td><\/tr>\n
      5<\/td>1Q<\/td>Output<\/td>Flip-flop 1 Q output<\/td><\/tr>\n
      6<\/td>1NOT-Q<\/td>Output<\/td>Flip-flop 1 NOT-Q output<\/td><\/tr>\n
      7<\/td>1CLR<\/td>Input<\/td>Flip-flop 1 clear (active LOW, sets Q=0)<\/td><\/tr>\n
      8<\/td>GND<\/td>Power<\/td>Ground<\/td><\/tr>\n
      9<\/td>2CLR<\/td>Input<\/td>Flip-flop 2 clear (active LOW)<\/td><\/tr>\n
      10<\/td>2NOT-Q<\/td>Output<\/td>Flip-flop 2 NOT-Q output<\/td><\/tr>\n
      11<\/td>2Q<\/td>Output<\/td>Flip-flop 2 Q output<\/td><\/tr>\n
      12<\/td>2PRE<\/td>Input<\/td>Flip-flop 2 preset (active LOW)<\/td><\/tr>\n
      13<\/td>2J<\/td>Input<\/td>Flip-flop 2 J input<\/td><\/tr>\n
      14<\/td>2K<\/td>Input<\/td>Flip-flop 2 K input<\/td><\/tr>\n
      15<\/td>2CLK<\/td>Input<\/td>Flip-flop 2 clock (falling edge)<\/td><\/tr>\n
      16<\/td>VCC<\/td>Power<\/td>Supply (5V)<\/td><\/tr>\n<\/table>","application_scenarios":"
        \n
      • Divide-by-2:<\/strong> J=K=1 (tie to VCC); CLK input; Q output = CLK\/2; cascaded for divide-by-4, -8, -16...<\/li>\n
      • T-Flip-Flop:<\/strong> Same as toggle mode; used for frequency division<\/li>\n
      • Data Latch:<\/strong> J=D (data), K=NOT-D; CLK falling edge latches D into Q; D-type flip-flop behavior<\/li>\n
      • Shift Register:<\/strong> 1Q connects to 2J; 1NOT-Q to 2K; serial data into 1J\/1K; two-stage shift register<\/li>\n<\/ul>","alternative_models":"\n
        Model<\/th>Manufacturer<\/th>Key Difference<\/th>Package<\/th>Supply<\/th><\/tr>\n
        74LS112N<\/td>TI\/Nexperia<\/td>Original TTL version with 5V-only supply, typical propagation delay 10-15ns<\/td>DIP-16<\/td>5V TTL<\/td><\/tr>\n
        74LS112D<\/td>TI\/Nexperia<\/td>Surface-mount SOIC version of LS with identical logic function<\/td>SOIC-16<\/td>5V TTL<\/td><\/tr>\n
        74HC112D<\/td>TI\/Nexperia<\/td>CMOS version with wide 2-6V supply range, lower power consumption and higher noise immunity<\/td>SOIC-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HC112N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HC family for prototyping and repair<\/td>DIP-16<\/td>2-6V CMOS<\/td><\/tr>\n
        74HCT112D<\/td>TI\/Nexperia<\/td>CMOS with TTL-compatible input levels, ideal for mixing with LS devices at 5V<\/td>SOIC-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n
        74HCT112N<\/td>TI\/Nexperia<\/td>Through-hole DIP version of HCT family for prototyping and repair<\/td>DIP-16<\/td>4.5-5.5V TTL-in<\/td><\/tr>\n<\/table>\n

        The 74112 is a Dual Negative-Edge-Triggered J-K Flip-Flop. Family variants span from the original LS TTL (5V only) to modern LVC\/AUP (down to 0.8V). HC and HCT versions offer 2-6V CMOS operation with HCT providing TTL-compatible input thresholds for mixed 5V systems. CD4000-series equivalents offer the widest 3-18V supply range at the cost of lower switching speed. DIP packages (N suffix) are through-hole; SOIC (D suffix) and TSSOP are surface-mount.<\/p>"},"_links":{"self":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7963","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/comments?post=7963"}],"version-history":[{"count":1,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7963\/revisions"}],"predecessor-version":[{"id":8169,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/posts\/7963\/revisions\/8169"}],"wp:attachment":[{"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/media?parent=7963"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/categories?post=7963"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/tags?post=7963"},{"taxonomy":"chip_brand","embeddable":true,"href":"https:\/\/materialparts.com\/ar\/wp-json\/wp\/v2\/chip_brand?post=7963"}],"curies":[{"name":"\u062f\u0628\u0644\u064a\u0648 \u0628\u064a","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}